Channels And Port Accesses - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

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Channels and Port Accesses

The Two Parts of a DMA Transfer

Direct Memory Access (DMA) Support

The DSP DMA controller has six paths, or channels, to transfer data among

the four standard ports (for DARAM, SARAM, external memory, and

peripherals). Each channel reads data from one port (the source) and writes

data to that same port or another port (the destination). Each channel has a

first-in, first-out (FIFO) buffer that allows the data transfer to occur in two

stages: port read access transfer of data from the source port to the channel

FIFO buffer and port write access transfer of data from the channel FIFO buffer

to the destination port (see Figure 16).

The set of conditions under which transfers occur in a channel is called the

channel context. Each of the six channels contains a register structure for

programming and updating the channel context (see Figure 17). User code

modifies the configuration registers. To transfer data, the contents of the

configuration registers are copied to the working registers, and the DMA

controller uses the working register values to control channel activity. The copy

from the configuration registers to the working registers occurs whenever user

code enables the channel (EN = 1 in DMA_CCR). In addition, if the

autoinitialization mode is on (AUTO_INIT = 1 in DMA_CCR), the copy occurs

between block transfers.

The DMA configuration registers consist of the following set:

Write access

n = 0, 1, 2, 3, 4, or 5

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