Omap5912 Power Management Software User Guide - Texas Instruments OMAP5912 Reference Manual

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OMAP5912 Power Management Software User Guide

SPRU753A
h) The DPLL clock restarts automatically.
i) The MPU and TC clocks restart automatically.
9) The OMAP5912 chip to sleep state transition
For OMAP5912 the MPU domain sleep state is not a true domain state in the
sense that it cannot be entered or exited without the intervention of another
device. An external device must shut down the MPU domain regulator.
The wake-up can be performed only through a power-up sequence by
asserting the OMAP5912 power up reset.
10) Set RNG_CONF_IDLE_MODE, bit 6 of the RESET_CONTROL register,
to 0 so that there is no waiting for RNG to enter the idle state to enter
CHIP_IDLE:
J
Command WR32 0xFFFE 1140 0x0000 003F
Note: By clearing bit 6 in RESET_CONTROL, the RNG idle acknowledge
is ignored. This implies that the RNG will not prevent the chip from entering
idle but the internal ring oscillators may still consume power. If bit 6 in RE-
SET_CONTROL is not cleared, then the RNG must be configured to shut
down its internal ring oscillators before allowing the system to idle. This
implies that the latency between awake and idle states is longer.
11) Disable the MPU watchdog timer by writing the sequence F5, A0 in the
TIMER_MODE register:
J
Command WR32 0xFFFE C808 0x0000 00F5
J
Command WR32 0xFFFE C808 0x0000 00A0
12) Disable the DSP watchdog timer by writing the sequence F5, A0 in the
TIMER_MODE register:
J
Command WR16 0xE100 6808 0x00F5
J
Command WR16 0xE100 6808 0x00A0
13) Configure the ARM_IDLECT1 register to turn off DPLL1, LCD, DMA,
ARMPER, internal timer, MPUI, ARMXOR, and MPU watchdog clocks
when the MPU enters idle state:
J
Command WR32 0xFFFE CE04 0x0000 17FF
14) Configure the ARM_IDLECT2 register to turn off the external GPIO clock:
J
Command WR32 0xFFFE CE08 0x0000 FDFF
OMAP5912 Power Management Software User Guide
Power Management 103