Logical Channel Preempting - Texas Instruments OMAP5912 Reference Manual

3.1.9

Logical Channel Preempting

SPRU755B
LCh Types Supporting this Feature LCh Types Supporting this Feature
A logical channel can be preempted on the element boundary, so that the
current element and any ongoing bursts are fully transferred before the
channel gets preempted.
Preemption occurs when a high-priority LCh suspends a low-priority LCh. This
happens if no other PChs are free when the high-priority LCh gets active. For
more details, see section 3.1.6, Logical Channel Scheduling.
A synchronized channel goes into an interleaved state once a DMA request
is served, and it waits for a new DMA request. It goes into a preempted state
once a higher priority logical channel is activated on the same physical
channel.
A nonsynchronized channel goes into a preempted state once a higher logical
channel is activated on the same physical channel.
A suspended (preempted) low-priority LCh always has a higher priority than
a lower priority LCh to be scheduled later. In other words, the preempted LCh
does not have to be rearbitrated. However, a suspended LCh takes over the
next free PCh. This means that the same PCh is not necessarily to be used
if the preempted LCh is of an LCh type supported by several PChs.
An active, preempted, synchronized LCh (the preempted LCh that received a
DMA request and was active before the preemption) does not need a new
DMA request. The LCh continues the transfer as soon as a PCh becomes free.
If new DMA requests are received when a synchronized LCh is preempted, an
event drop is issued on the second new DMA request and the LCH is disabled.
If the DROP_IE bit is set to 1 in the DMA_CICR register, then an interrupt is
generated and the DROP bit in the DMA_CSR register is set.
The content in the FIFOs in the physical channels is always transferred before
the logical channel releases the physical channel. When a physical channel
is preempted, it is always on the source element boundary. Therefore, the
physical channel drains the FIFO data to the destination before the LCh
releases the PCh.
2D P
√ √
Direct Memory Access (DMA) Support
System DMA
PD G D
√ N/A
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