Tipb Router; Peripheral Instantiation - Texas Instruments OMAP5912 Reference Manual

2.12

Peripheral Instantiation

Table 9. Private Peripherals Instantiation
OMAP 5912
Peripheral
Interface
3 DSP level 2 TIPB
interrupt
handler
ULPD (clock TIPB
and reset)
OMAP5912 TIPB
configuration
Secure Wrapper
watchdog OCP
32-kHz Wrapper
watchdog OCP
2 MPU level 2 TIPB
interrupt
handlers
SHA_1 Wrapper
accelerator OCP
RNG random Wrapper
generator OCP
DES/3DES Wrapper
OCP
System DMA Wrapper
handler OCP
† Address bus alignment:
Byte: The least significant bit of the peripheral address bus corresponds to a byte address in the peripheral.
16-bit: The least significant bit of the peripheral address bus corresponds to a 16-bit address in the peripheral.
32-bit: The least significant bit of the peripheral address bus corresponds to a 32-bit address in the peripheral.
SPRU758A
Instantiation
Address Bus Address Bus
{
Alignment
Data
Byte 16
Byte 16
Byte 32
Byte 32
Byte 32
Byte 32
Byte 32
Byte 32
Byte 32
Byte 32

TIPB Router

Access Size Access Size
8b 16b 32b
− R − Private DSP
− R − Private MPU
− − R Private MPU
− R R Private MPU
− R R Private MPU
− − R Private MPU
− − R Private MPU
− − R Private MPU
− − R Private MPU
− − R Private MPU
Peripheral Interconnects
Layer 4 Interconnect
35