Dsp And Mpu Os Timer; Reading Os Timer Values; Dsp And Mpu Os Timer Input Clocks - Texas Instruments OMAP5912 Reference Manual

OMAP3.2 Operating System Timer
3.2

DSP and MPU OS Timer

3.3

Reading OS Timer Values

3.4

DSP and MPU OS Timer Input Clocks

3.4.1 Configuration of the Input Clock for DSP 32-Bit OS Timers
22 Timers
If the autoreload (AR) bit is set in DSP_CNTL_TIMER or MPU_CNTL_TIMER,
a new value (from the load register) is loaded into the timer when it passes
through zero.
If the AR bit is reset, the timer decrements from the loaded value to zero and
then stops.
The timer values can be read from the respective DSP or MPU read timer
registers either on-the-fly or after the timer is stopped.
For the MPU, MPU_READ_TIMER is a 32-bit register and can be read
-
directly.
By contrast, the data width of the DSP is only 16 bits. To read the value
-
of the DSP OS timers correctly, the first access must be to the upper
16 bits.
When the upper read occurs, the lower 16 bits are simultaneously stored
in a temporary register. An access to the lower 16 bits provides the content
of this temporary register as the read result. A read from
DSP_READ_TIMER_HI followed by a read from DSP_READ_TIM-
ER_LO provides the correct DSP OS timer read result.
This section describes clocking for the DSP and MPU OS timers.
The input clock reference for the DSP timer modules is controlled from the
clock generation and reset module. Programming the TIMXO bit of the DSP
prescaler selection register DSP_CKCTL in the clock module selects between
two possible clock sources:
Programming the TIMXO bit to 0 selects the main input reference clock as
-
the clock reference for the DSP timers.
Programming the TIMXO bit to 1 selects the output from the DPLL1
-
module as the source for the DSP 32-bit OS timers.
The default is referenced from DPLL1. When operating from DPLL1, it is
recommended to stop the DSP OS timer before programming a change to the
DPLL1 frequency divisor. See Clock Generation and Reset Management in
the Multimedia Processor OMAP 3.2 Subsystem Reference Guide
(SPRU749) for details on DSP_CKCTL and on programming the DPLL1
module.
SPRU759B