Clock Distribution In Omap5912; Clock Inputs To Ulpd - Texas Instruments OMAP5912 Reference Manual

Figure 14. 32-kHz and System Clock Scheme
RTC power split
CLK32K_IN
OSC32K_IN
SYS_CLK_IN
On at reset
(OMAP5910
legacy)
RESET_MODE
OSC1_IN
XOA
OSC1_OUT
OMAP5912 configuration register:
CONF_OSC1_PWRDN_R: =0
(= value at reset): 12 MHz osc powered on
= 1: The 12 MHz PWRDN pin is activated
(PWRDN = 1) meaning that the internal
rfeedback resistor of the oscillator is disabled
5.10

Clock Distribution in OMAP5912

5.10.1

Clock Inputs to ULPD

SPRU751A
EXT_CLK
CLK32K_OUT
SYSTEM_CLOCK
OSC_EXTCLOCK
Y
OS1401
GZ
RF
PWRDN
XIA LOGIC:
OS1141
The ultralow-power device (ULPD) manages transitions between deep sleep
mode, big sleep mode, and awake mode. In each mode, the clocks from the
ULPD are gated or ungated either by hardware or by software. The ULPD
module is also in charge of managing communication with an external power
management device for dynamic voltage scaling. Communication is ensured
through LOW_POWER outputs from OMAP5912.
Figure 15 provides an overview of ULPD clocking. See OMAP5912
Multimedia Processor Power Management Reference Guide (literature
number SPRU753) for further details on the ULPD.
OMAP5912 configuration
Default path
32 kHz clock
domain
CK_REF
Clock
management
ULPD FSM
ULPD
OSCILLATOR_STOP
OMAP5912 configuration register:
FUNC_MUX_CTRL_B[20:18]:
If 001: The 12 MHz osc PWRDN pin
is activated (PWRDN = 1).
000 = value at reset)
OMAP5912 configuration register:
CONF_OSC1_GZ_R:
= 0 (= value at reset)
= 1: The 12 MHz osc GZ pin is
activated (GZ = 1).
OMAP5912 Clock Architecture
GP timers
(one mux by GP timer with
independent control from
OMAP5912 configuration)
OMAP3.2
Clocks 39