Status Fifo Register (Sfregl, Sfregh) - Texas Instruments OMAP5912 Reference Manual

6.4.2

Status FIFO Register (SFREGL, SFREGH)

Table 100. Status FIFO Register Low (SFREGL)
Bit Name
7:0 SFREGL
Table 101. Status FIFO Register High (SFREGH)
Bit Name
7:4 −
3:0 SFREGH
Table 102. BOF Control Register (BLR)
Bit Name
7 STS_FIFO_RESET
6 XBOF_TYPE
5:0 −
SPRU760B
IrDA modes only. The frame lengths of received frames are written into the
status FIFO. This information can be read from the SFREGL and SFREGH
registers. These registers do not physically exist. The least-significant bits are
read from SFREGL, and the most-significant bits are read from SFREGH.
Reading these registers does not alter the status FIFO read pointer. These
registers must be read before the pointer is incremented by reading the
SFLSR.
Offset Address (hex): 0x0C x S and read
Function
LSB part of the frame length
Offset Address (hex): 0x0D x S and read
Function
Reserved
MSB part of the frame length
Offset Address (hex): 0x0E x S and LCR[7] = 0
IrDA modes only. BLR[6] is used to select whether 0xC0 or 0xFF start patterns
are to be used when multiple start flags are required in SIR mode. If only one
start flag is required, the start pattern is always 0xC0. If n start flags are
required, either (n−1) 0xC0 or (n−1) 0xFF flags are sent, followed by a single
0xC0 flag immediately preceding the first data byte.
Function
Status FIFO reset. This bit is self-clearing.
SIR xBOF select
0: 0xFF.
1: 0xC0.
Reserved
Offset Address (hex): 0x12 x S and LCR[7] = 0
UARTs
R/W Reset
R Unknown
R/W Reset
R 0x0
R Unknown
R/W Reset
R/W 0
R/W 1
R 000000
Serial Interfaces 169