Omap5912/5910 Software And Hardware Compatibility - Texas Instruments OMAP5912 Reference Manual

Table 9. Parallel Observability Multiplexing Signals (Continued)
L19 SYS_CLK_OUT
8
J18 DLL_PMT_DCB[7]
J19 DLL_PMT_DCB[6]
8
J14 DLL_PMT_DCB[5]
K18 DLL_PMT_DCB[4]
K19 DLL_PMT_DCB[3]
K15 DLL_PMT_DCB[2]
K14 DLL_PMT_DCB[1]
L19 DLL_PMT_DCB[0]
2.4

OMAP5912/5910 Software and Hardware Compatibility

SPRU752B
CONF_OBS_MUX_SEL_R Value
OMAP3.2 DPLL
enable
9
ULPD clock switch
status
UART2 functional
clock (from system
clock)
9
Internal 32k clock
(distributed to
peripherals)
Internal system clock Reserved
Internal 32k clock
(feeding ULPD)
32k oscillator
PWRDN
12-MHz oscillator GZ Reserved
12-MHz oscillator
PWRDN
The device resets based on the RESET_MODE pin are forced either to the
functional multiplexing mode 000, with the appropriate pullups or pulldowns
configured and enabled to preserve the OMAP5910 pinout reset condition, or
to the new reset mode 1. The multiplexing per pin remains software compatible
with OMAP5910 and is controlled by the same 3-bit field (eight mux modes
possible).
BIST GO CHIP_NWAKEUP
10
RNG functional clock
Reserved
10
Reserved
Reserved
Reserved
Reserved
Configuration
Initialization 33