Dma Transfers (Dma Mode 1, 2, Or 3) - Texas Instruments OMAP5912 Reference Manual

UARTs

DMA Transfers (DMA Mode 1, 2, or 3)

Figure 72. Receive FIFO DMA Request Generation (32 Characters)
RX buffer
max
Programmable
threshold
Zero level
DMA Active periods,this
does not represent the DMA
signalling
186 Serial Interfaces
Figure 72 through Figure 75 show the supported DMA operations.
Data received while DMA
operation ongoing
In receive mode, a DMA request is generated as soon as the receive FIFO
reaches its threshold level as defined in the trigger level register (TLR). (See
Table 88.) This request is deasserted when the system DMA reads the number
of bytes defined by the threshold level.
In transmit mode, a DMA request is automatically asserted when the FIFO is
empty. This request is deasserted when the system DMA writes the number
of bytes defined by the number of spaces in the trigger level register (TLR). If
an insufficient number of characters is written, the DMA request remains
active.
32 characters
Time
SPRU760B