Control Mode Register - Texas Instruments OMAP5912 Reference Manual

TIPB Bridge
4.1

Control Mode Register

Table 13. Control Mode Register (CMR)—Value at Reset is 0xFE4D
CMR
[15−0]
Designation
15−9 Time-out (6:0)
8−6 Wait state
(strobe 1)
5−3 Wait state
(strobe 0)
2 CPU priority
1 Bus error
0 Mode
50 DSP Subsystem
The control mode register (CMR) indicates the shared-access mode/host-only
mode (SAM/HOM) status of the MPUI and bus error condition status for
accesses to the TIPB bridge. It also controls CPU priority versus the MPUI and
DMA for accesses to peripherals on the TIPB bridge.
Description
Strobe cycles
(0-127)
Strobe1 length
(low, medium, high
bits)
Strobe 0 length
(low, medium, high
bits)
Priority modes
Application flag
error
SAM or HOM
-
Mode bit
This bit is a read-only indication of whether the MPUI is in host-only mode
(HOM) or in single-access mode (SAM). HOM and SAM are described in
Section 3.6, External Memory Interface.
-
Bus error
This bit is set to 1 if the TIPB bridge generates a bus error (because of a
time-out condition or SAM/HOM change error), indicating that an error sig-
nal that can read this bit to identify the source of the error condition has
been sent to the DSP CPU. The bit is cleared upon read by the DSP CPU.
This bit cannot be read during HOM (always registers as zero during
HOM).
Reset
Value
CPU Access
0x7F Read/Write
0 Read/Write
1 Read/Write
1 Read/Write
0 Read/Clear
1 (HOM) Read
MPU Access
Read
Read
Read
Read
Read (0 in HOM)
Read
SPRU750A