Mode Functionality - Texas Instruments OMAP5912 Reference Manual

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Mode Functionality

TCRR Timing Value

Load register

The timer is an upward counter that can be started and stopped at any time

through the timer control register (TCLR ST bit). The timer counter register

(TCRR) can be loaded when stopped or on the fly (while counting). TCRR can

be loaded directly by a TCRR write access with the new timer value. TCRR can

also be loaded with the value held in the timer load register TLDR by a trig

TTGR written value. The timer counter register TCRR value can be read when

stopped or captured on the fly by a TCRR read access. The timer is stopped

and the counter value set to 0 when the modules reset is asserted. The timer

is maintained in stop after reset is released. When the timer is stopped, TCRR

is frozen and it can be restarted from the frozen value, unless TCRR has been

reloaded with a new value.

In one-shot mode (TCLR AR bit =0), the counter is stopped after counting

overflow (counter value remains at zero).

When autoreload mode is enabled (TCLR AR bit =1), the TCRR is reloaded

with the timer load register (TLDR) value after a counting overflow. An interrupt

can be issued on overflow if the overflow interrupt enable bit is set in the timer

interrupt enable register (TIER OVF_IT_ENA bit =1). A dedicated output pin

(timer PWM) can be programmed through TCLR (TRG and PT bits) to

generate one positive pulse (prescaler duration) or to invert the current value

(toggle mode) when an overflow occurs.

Figure 5 shows the TCRR timing value.

Trig register

Counter register

Dual-Mode Timer

reset pulse is

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