Mpu Interface - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

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MPU Interface

Table 16. Idle Status Register (ISTR)

Not connected

Reserved idle status

EMIF idle status

DPLL idle status

Peripherals idle status

Cache idle status

DMA idle status

CPU idle status

MPU Interface

DSP Subsystem

The DSP must not attempt to read the ISTR while the DPLL domain

is idled because this causes a time-out error.

The MPU interface (MPUI) is a 16-bit parallel port that allows the MPU and the

system DMA controller to communicate with the DSP and its peripherals,

facilitating software downloads and data transfers. For additional information,

please see OMAP5912 Multimedia Processor OMAP3.2 Subsystem Reference

Guide (literature number SPRU749).

The MPUI provides the MPU with access to the full memory space of the DSP

(16M bytes). In addition, the MPUI allows the MPU to access devices on the

DSP public peripheral bus through duplicate memory-mapped peripheral

registers in the MPU address space. The MPU domain can also access the

control registers of the TIPB bridge module and the CLKM2 configuration

registers. The DSP private peripherals are not accessible via the MPUI.

MPUI transfers are facilitated by an auxiliary channel of the DSP subsystem

DMA controller; however, this dedicated DMA channel is preconfigured and

need not be user-configured for MPUI support.

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