Watchdog Module Under Emulation; Watchdog Timer Registers - Texas Instruments OMAP5912 Reference Manual

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32-Bit Watchdog Timer General Overview
1.10

Watchdog Module Under Emulation

1.11

Watchdog Timer Registers

Table 5.
Watchdog Timer Registers
Name
WIDR
RESERVED
RESERVED
RESERVED
WD_SYSCONFIG
WD_SYSSTATUS
RESERVED
RESERVED
RESERVED
WCLR
WCRR
WLDR
WTGR
To keep mapping compatibility between 32-bit watchdog and dual-mode timer modules.
14
Timers
During emulation mode, the 32-bit watchdog can/cannot continue to run
according to the value of the EMUFREE bit of the system configuration register
(WD_SYSCONFIG).
If EMUFREE is 1, timer execution is not stopped in emulation mode and a reset
pulse is still generated when overflow is reached.
If EMUFREE is 0, counters (prescaler/timer) are frozen and increment starts
again after exit from emulation mode.
Address of register: Start address + Address offset
Registers width: 32 bits (can be accessed as 32 bits or as 2 x 16 bits –
OCP access)
Table 5 lists the 32-bit watchdog timer registers. Table 6 through Table 14
describe the register bits.
Base Address = 0xFFFE B000
Description
Watchdog HW revision (ID)
Reserved
Reserved
Reserved
Watchdog system configuration
Watchdog status
Reserved
Reserved
Reserved
Watchdog control
Watchdog counter
Watchdog load
Watchdog trigger
R/W
Offset
R
0x00
-
0x04
-
0x08
-
0x0C
R/W
0x10
R
0x14
-
0x18
-
0x1C
-
0x20
R/W
0x24
R/W
0x28
R/W
0x2C
R/W
0x30
SPRU759B

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