Clock And Reset Module; Programming Model; Ocpi Registers (Mpu Address: Fffe:c320); Ocpt Registers (Mpu Address: Fffe:cc00) - Texas Instruments OMAP5912 Reference Manual

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Clock and Reset Module

On-Chip/Off-Chip Memory and Peripheral Access Latencies

The clock and reset module manages the clock and reset signals for the SSI

interconnect module and the SSI (SSR and SST) module. This module

resynchronizes reset signals and implements the AUTOIDLE mechanism for

the SSI interconnect module.

The OCPI interface allocates memory spaces to the initiator in secure mode

and logs unauthorized data transfers and aborts.

See the OMAP3.2 Technical Reference Manual (SWPU019E) for additional

information.

The OCP-T2 interface manages priority between concurrent data transfers

and logs unauthorized data transfers and aborts.

See the OMAP3.2 Technical Reference Manual (SWPU019E) for additional

information.

To avoid free-running clocks in the OCP and the SSI interconnects, it is

possible to shut off the clocks when no data transfer is in progress. This feature

is called autoidle.

Bit [25] of MOD_CONF_CTRL_1 in OMAP5912 configuration enables the

OCP interconnect to use its autoidle features.

Reset value is 0x1.

Bit [26] of MOD_CONF_CTRL_1 in OMAP5912 configuration enables the SSI

interconnect to use its autoidle features.

Reset value is 0x1.

Table 15 and Table 16 list latencies for accesses either to off-chip memories

or on-chip memories and peripherals.

All accesses are calculated assuming a 200-MHz MPU and DSP clocks.

Table 15 lists the OMAP3.2 timing parameters.

Peripheral Interconnects

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