Data Packing - Texas Instruments OMAP5912 Reference Manual

DSP DMA
4.10

Data Packing

Table 101. DMA Controller Ports
140 Direct Memory Access (DMA) Support
a(0) = SA
a(i) = a(i – 1) + 1 if (I mod ES) = 0 and (i mod FS) ⎯0, 1 . i . BS – 1
a(i) = a(i – 1) + EI if (i mod ES) = 0 and (i mod FS) ⎯0, 1 . i . ℜS – 1
a(i) = a(i – 1) + FI if (i mod FS) = 0, 1 . i . BS – 1
where:
a(i) is the address of the byte number i within the transfer.
SA is the start address of the transfer.
BS is the block size in bytes.
ES is the element size in bytes.
EI is the element index in bytes, specified in a configuration register, –32768.
EI . 32767.
FS is the frame size in bytes, FS = ES x EN.
FI is the frame index in bytes, specified in a configuration register, –32768.
FI . 32767.
The five DMA controller ports have various widths and support various sizes
of data accesses as listed in Table 101.
DMA Port
SARAM
DARAM
EMIF
Peripheral
MPUI
A DMA channel has the ability to:
Pack several consecutive element transfers into wider accesses. For
-
example, if the element size is 16 bits, the 32-bit-wide SARAM port can
pack two accesses so that 4 bytes at a time are written into the channel
FIFO. Packing effectively reduces the frequency at which that channel
must be serviced by the port service chain. This can reduce overhead and
improve channel throughput in some cases. Packing options are
determined by port access capabilities and element size. Packing at the
source or destination port can be disabled by software control.
Port Width Access Sizes Supported (bytes)
32
32
32
16
16
2, 4
2, 4
1, 2, 4
2
2
SPRU755B