Mpu/Dsp Tipb Bridge To Peripherals; Peripherals To Mpu/Dsp Tipb Bridge - Texas Instruments OMAP5912 Reference Manual

Figure 4. Transfer from Host to Peripheral

Peripherals to MPU/DSP TIPB Bridge

Figure 5. Transfer from Peripheral to Host
Bus allocation
module
peripherals to MPU
TIPB router
Note: Default value: To simplify the TIPB router implementation and reduce the toggling on buses, a default value is returned to
the host that does not access the peripheral.
2.4.2 16-bit Accesses on 32-Bit Atomic Registers
SPRU758A
MPU TIPB bridge signals
DSP TIPB bridge signals
All peripherals can send data back on a dedicated bus (one bus per
peripheral—8-, 16-, or 32-bit according to each peripheral requirement), either
to the MPU or to the DSP.
PERIPHERAL
MPU TIPB bridge
syncronization
MPU TIPB router
signals
There is no protection inside the dynamic switch to ensure the atomic reading
or writing of one 32-bit register with two 16-bit accesses. The nonoverlapping
requests from the two hosts must be controlled in the software.
PERIPHERAL
Bus allocation
module
MPU/DSPTIPB
bridge to peripherals
PERIPHERAL
DSP TIPB bridge
syncronization
DSP TIPB router
signals
Peripheral Interconnects
Layer 4 Interconnect
Bus allocation
module
peripherals to DSP
TIPB router
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