Fifo Polled Mode Operation; Fifo Dma Mode Operation; Dma Signaling - Texas Instruments OMAP5912 Reference Manual

6.6.4

FIFO Polled Mode Operation

6.6.5

FIFO DMA Mode Operation

DMA Signaling

SPRU760B
In FIFO polled mode (FCR [0] = 0, relevant interrupts disabled via interrupt
enable register (IER)), the status of the receiver and transmitter are checked
by polling the line status register (LSR). This mode is an alternative to the FIFO
interrupt mode of operation in which the status of the receiver and transmitter
is automatically known by means of interrupts sent to the LH.
The four modes of DMA operation, DMA modes 0/1/2/3, are selected as
follows:
When SCR[0] = 0: Setting FCR[3] to 0 enables DMA mode 0.
Setting FCR[3] to 1 enables DMA mode 1.
When SCR[0] = 1: SCR[2:1] determine DMA mode 0 to 3 according to
supplementary control register (SCR) description.
For example:
If no DMA operation is desired: Set SCR[0] to 1 and SCR[2:1] to 00
-
(FCR[3] is discarded).
If DMA mode 1 is desired: Either set SCR[0] to 0 and FCR[3] to 1 or set
-
SCR[0] to 1 and SCR[2:1] to 01 (FCR[3] is discarded).
If the FIFOs are disabled (FCR[0] = 0), DMA occurs in single-character
transfers.
When DMA mode 0 has been programmed, the signals associated with DMA
operation are not active.
UARTs
Serial Interfaces 185