Dual-Mode Timer Under Emulation; Accessing Registers; Programming Timer Registers; Reading Timer Registers - Texas Instruments OMAP5912 Reference Manual

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Table 31. Value and Corresponding Interrupt Period

Dual-Mode Timer Under Emulation

During emulation mode, the dual-mode timer continues to run according to the

value of the EMUFREE bit of the timer OCP configuration register

(TIOCP_CFG).

If EMUFREE is 1, timer execution is not stopped in emulation mode and the

interrupt assertion is still generated when overflow is reached.

If EMUFREE is 0, the prescaler and timer are frozen and both resume on exit

from emulation mode. The asynchronous input pin is internally synchronized

on two timer-clock rising edges.

All registers are 32 bits wide, accessible via OCP interface with 16-bit or 32-bit

OCP access (read/write).

The host uses the OCP bus protocol to write the TLDR, TCRR, TIER, TISR,

TCLR, TIOCP_CFG, TWER, TTGR, TSICR, and TMAR registers

synchronously with the timer interface clock.

Because the timer registers are 32-bit wide, 16-bit wide access mode requires

two consecutive write operations (16 LSBs followed by 16 MSBs).

In 16-bit access mode, reading the LSBs from the timer counter register

(TCRR) captures the current timer counter value. This must be followed by

reading the 16 MSBs.

Interrupt Period

Dual-Mode Timer

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