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Texas Instruments TMS320C67X+ DSP manual available for free PDF download: Reference Manual
Texas Instruments TMS320C67X+ DSP Reference Manual (465 pages)
DSP and CPU Instruction Set
Brand:
Texas Instruments
| Category:
Computer Hardware
| Size: 1 MB
Table of Contents
Read this First
3
Table of Contents
5
Introduction
19
TMS320 DSP Family Overview
19
TMS320C6000 DSP Family Overview
19
Typical Applications for the TMS320 Dsps
20
Tms320C67X DSP Features and Options
21
Tms320C67X DSP Architecture
24
Tms320C67X DSP Block Diagram
24
Central Processing Unit (CPU)
25
Internal Memory
25
Memory and Peripheral Options
25
Control Registers
25
CPU Data Paths and Control
27
Introduction
28
General-Purpose Register Files
28
Tms320C67X CPU Data Paths
29
Storage Scheme for 40-Bit Data in a Register Pair
30
Bit/64-Bit Register Pairs
30
Functional Units
31
Functional Units and Operations Performed
31
Register File Cross Paths
32
Memory, Load, and Store Paths
32
Data Address Paths
33
Control Register File
33
Register Addresses for Accessing the Control Registers
34
Pipeline/Timing of Control Register Accesses
35
Addressing Mode Register (AMR)
36
Addressing Mode Register (AMR) Field Descriptions
36
Block Size Calculations
38
Control Status Register (CSR)
39
PWRD Field of Control Status Register (CSR)
39
Control Status Register (CSR) Field Descriptions
40
Interrupt Clear Register (ICR)
42
Interrupt Clear Register (ICR) Field Descriptions
42
Interrupt Enable Register (IER)
43
Interrupt Enable Register (IER) Field Descriptions
43
Interrupt Flag Register (IFR)
44
Interrupt Flag Register (IFR) Field Descriptions
44
Interrupt Return Pointer Register (IRP)
45
Interrupt Set Register (ISR)
46
Interrupt Set Register (ISR) Field Descriptions
46
Interrupt Service Table Pointer Register (ISTP)
47
Interrupt Service Table Pointer Register (ISTP) Field Descriptions
47
Nonmaskable Interrupt (NMI) Return Pointer Register (NRP)
48
E1 Phase Program Counter (PCE1)
48
NMI Return Pointer Register (NRP)
48
Control Register File Extensions
49
Floating-Point Adder Configuration Register (FADCR)
49
Floating-Point Auxiliary Configuration Register (FAUCR)
49
Floating-Point Multiplier Configuration Register (FMCR)
49
Floating-Point Adder Configuration Register (FADCR) Field Descriptions
50
Floating-Point Auxiliary Configuration Register (FAUCR)
53
Floating-Point Auxiliary Configuration Register (FAUCR) Field Descriptions
53
Floating-Point Multiplier Configuration Register (FMCR)
57
Floating-Point Multiplier Configuration Register (FMCR) Field Descriptions
57
Instruction Set
61
Instruction Operation and Execution Notations
62
Instruction Syntax and Opcode Notations
67
Overview of IEEE Standard Single- and Double-Precision Formats
69
IEEE Floating-Point Notations
70
Single-Precision Floating-Point Fields
71
Special Single-Precision Values
71
Double-Precision Floating-Point Fields
72
Hexadecimal and Decimal Representation for Selected Single-Precision Values
72
Special Double-Precision Values
73
Hexadecimal and Decimal Representation for Selected Double-Precision Values
73
Delay Slots
74
Delay Slot and Functional Unit Latency
75
Parallel Operations
76
Basic Format of a Fetch Packet
76
Fully Serial P-Bit Pattern in a Fetch Packet
77
Fully Parallel P-Bit Pattern in a Fetch Packet
77
Example Parallel Code
78
Branching into the Middle of an Execute Packet
78
Partially Serial P-Bit Pattern in a Fetch Packet
78
Conditional Operations
79
Registers that Can be Tested by Conditional Operations
79
Resource Constraints
80
Same Instruction Cycle
80
Constraints on Instructions Using the same Functional Unit
80
Constraints on the same Functional Unit Writing in the same Instruction Cycle
80
Constraints on Cross Paths (1X and 2X)
81
Constraints on Long (40-Bit) Data
83
Constraints on Register Reads
84
Constraints on Register Writes
85
Examples of the Detectability of Write Conflicts by the Assembler
85
Constraints on Floating-Point Instructions
86
Addressing Modes
90
Linear Addressing Mode
90
Circular Addressing Mode
91
LDW Instruction in Circular Mode
91
Syntax for Load/Store Address Generation
92
ADDAH Instruction in Circular Mode
92
Indirect Address Generation for Load/Store
93
Address Generator Options for Load/Store
93
Instruction Compatibility
94
Instruction Descriptions
94
Relationships between Operands, Operand Size, Signed/Unsigned
96
Functional Units, and Opfields for Example Instruction (ADD)
96
ABS (Absolute Value with Saturation)
98
ABSDP (Absolute Value, Double-Precision Floating-Point)
100
ABSSP (Absolute Value, Single-Precision Floating-Point)
102
ADD Add Two Signed Integers Without Saturation
104
ADDAB (Add Using Byte Addressing Mode)
108
ADDAD (Add Using Doubleword Addressing Mode)
110
ADDAH (Add Using Halfword Addressing Mode)
112
ADDAW (Add Using Word Addressing Mode)
114
ADDDP Add Two Double-Precision Floating-Point Values
118
ADDK (Add Signed 16-Bit Constant to Register)
119
ADDSP (Add Two Single-Precision Floating-Point Values)
120
ADD2 (Add Two 16-Bit Integers on Upper and Lower Register Halves)
125
AND (Bitwise AND)
127
B (Branch Using a Displacement)
129
B (Branch Using a Register)
129
Program Counter Values for Example Branch Using a Displacement
130
Program Counter Values for Example Branch Using a Register
132
B IRP (Branch Using an Interrupt Return Pointer)
133
Program Counter Values for B IRP Instruction
134
B NRP (Branch Using NMI Return Pointer)
135
Program Counter Values for B NRP Instruction
136
CLR Clear a Bit Field
138
CMPEQ (Compare for Equality, Signed Integers)
140
CMPEQDP (Compare for Equality, Double-Precision Floating-Point Values)
142
CMPEQSP (Compare for Equality, Single-Precision Floating-Point Values)
144
CMPGT (Compare for Greater Than, Signed Integers)
146
CMPGTU (Compare for Greater Than, Unsigned Integers)
153
CMPLT Compare for Less Than, Signed Integers
155
CMPLTDP Compare for Less Than, Double-Precision Floating-Point Values
158
CMPLTSP Compare for Less Than, Single-Precision Floating-Point Values
160
CMPLTU (Compare for Less Than, Unsigned Integers)
162
DPINT (Convert Double-Precision Floating-Point Value to Integer)
164
Dpsp
166
Single-Precision Floating-Point Value)
166
Dptrunc
168
Integer with Truncation)
168
EXT Extract and Sign-Extend a Bit Field
170
EXTU Extract and Zero-Extend a Bit Field
174
IDLE Multicycle NOP with No Termination until Interrupt
176
INTDP (Convert Signed Integer to Double-Precision Floating-Point Value)
177
INTDPU Convert Unsigned Integer to Double-Precision Floating-Point Value
180
INTSP (Convert Signed Integer to Single-Precision Floating-Point Value)
181
INTSPU (Convert Unsigned Integer to Single-Precision Floating-Point Value)
182
Ldb(U)
183
Register Offset
183
Data Types Supported by LDB(U) Instruction
183
LDB(U) Load Byte from Memory with a 15-Bit Unsigned Constant Offset
186
Data Types Supported by LDB(U) Instruction (15-Bit Offset)
186
Lddw
188
Register Offset
188
Ldh(U)
191
Register Offset
191
Data Types Supported by LDH(U) Instruction
191
LDH(U) (Load Halfword from Memory with a 15-Bit Unsigned Constant Offset)
195
Data Types Supported by LDH(U) Instruction (15-Bit Offset)
195
Ldw
196
Register Offset
196
LDW (Load Word from Memory with a 15-Bit Unsigned Constant Offset)
196
LMBD Leftmost Bit Detection
202
MPY (Multiply Signed 16 LSB by Signed 16 LSB)
203
MPYDP (Multiply Two Double-Precision Floating-Point Values)
205
MPYH (Multiply Signed 16 MSB by Signed 16 MSB)
207
MPYHL (Multiply Signed 16 MSB by Signed 16 LSB)
209
MPYHLU (Multiply Unsigned 16 MSB by Unsigned 16 LSB)
211
MPYHSLU (Multiply Signed 16 MSB by Unsigned 16 LSB)
212
MPYHULS (Multiply Unsigned 16 MSB by Signed 16 LSB)
215
MPYHUS (Multiply Unsigned 16 MSB by Signed 16 MSB)
216
MPYID (Multiply 32-Bit by 32-Bit into 64-Bit Result)
218
MPYLH (Multiply Signed 16 LSB by Signed 16 MSB)
221
MPYLHU (Multiply Unsigned 16 LSB by Unsigned 16 MSB)
223
MPYLSHU (Multiply Signed 16 LSB by Unsigned 16 MSB)
224
MPYLUHS (Multiply Unsigned 16 LSB by Signed 16 MSB)
225
MPYSP (Multiply Two Single-Precision Floating-Point Values)
226
Mpyspdp
228
Mpysp2Dp
230
Double-Precision Result
230
MPYSU (Multiply Signed 16 LSB by Unsigned 16 LSB)
232
MPYU (Multiply Unsigned 16 LSB by Unsigned 16 LSB)
234
MPYUS (Multiply Unsigned 16 LSB by Signed 16 LSB)
236
MV Move from Register to Register
238
MVC Move between Control File and Register File
240
Register Addresses for Accessing the Control Registers
242
MVK (Move Signed Constant into Register and Sign Extend)
243
Mvkl
247
NEG (Negate)
249
NOP No Operation
250
NORM Normalize Integer
252
NOT Bitwise NOT
254
OR Bitwise or
255
RCPDP (Double-Precision Floating-Point Reciprocal Approximation)
257
RCPSP (Single-Precision Floating-Point Reciprocal Approximation)
259
Rsqrdp
261
Rsqrsp
263
SADD Add Two Signed Integers with Saturation
266
SAT Saturate a 40-Bit Integer to a 32-Bit Integer
268
SET Set a Bit Field
270
SHL Arithmetic Shift Left
273
SHR Arithmetic Shift Right
276
SHRU Logical Shift Right
278
Smpy
279
Smpyhl
282
Smpylh
284
Spdp
286
SPINT (Convert Single-Precision Floating-Point Value to Integer)
288
Sptrunc
290
SSHL Shift Left with Saturation
292
SSUB (Subtract Two Signed Integers with Saturation)
294
Stb
296
Register Offset
296
STB Store Byte to Memory with a 15-Bit Unsigned Constant Offset
298
Sth
300
Register Offset
300
STH Store Halfword to Memory with a 15-Bit Unsigned Constant Offset
304
Stw
305
Register Offset
305
STW Store Word to Memory with a 15-Bit Unsigned Constant Offset
308
SUB Subtract Two Signed Integers Without Saturation
309
SUBAB (Subtract Using Byte Addressing Mode)
313
SUBAH (Subtract Using Halfword Addressing Mode)
315
SUBAW (Subtract Using Word Addressing Mode)
316
SUBC (Subtract Conditionally and Shift-Used for Division)
318
SUBDP Subtract Two Double-Precision Floating-Point Values
322
SUBSP Subtract Two Single-Precision Floating-Point Values
324
SUBU (Subtract Two Unsigned Integers Without Saturation)
326
SUB2 Subtract Two 16-Bit Integers on Upper and Lower Register Halves
328
XOR Bitwise Exclusive or
330
ZERO Zero a Register
332
Pipeline
333
Pipeline Operation Overview
334
Fetch
334
Pipeline Stages
334
Decode
335
Fetch Phases of the Pipeline
335
Decode Phases of the Pipeline
336
Execute
337
Execute Phases of the Pipeline
337
Pipeline Operation Summary
338
Pipeline Phases
338
Pipeline Operation: One Execute Packet Per Fetch Packet
338
Operations Occurring During Pipeline Phases
339
Pipeline Phases Block Diagram
342
Execute Packet in Figure 4−7
343
Pipeline Execution of Instruction Types
344
Execution Stage Length Description for each Instruction Type
344
Single-Cycle Instructions
348
Single-Cycle Instruction Phases
348
Single-Cycle Instruction Execution Block Diagram
348
Single-Cycle Instruction Execution
348
16 Y 16-Bit Multiply Instructions
349
Multiply Instruction Phases
349
Multiply Instruction Execution Block Diagram
349
Bit Multiply Instruction Execution
349
Store Instructions
350
Store Instruction Phases
350
Store Instruction Execution
350
Store Instruction Execution Block Diagram
351
Load Instructions
352
Load Instruction Phases
352
Load Instruction Execution
352
Load Instruction Execution Block Diagram
353
Branch Instructions
354
Branch Instruction Phases
354
Branch Instruction Execution
354
Branch Instruction Execution Block Diagram
355
Two-Cycle DP Instructions
356
Two-Cycle DP Instruction Phases
356
Two-Cycle DP Instruction Execution
356
Four-Cycle Instructions
357
Four-Cycle Instruction Phases
357
Four-Cycle Instruction Execution
357
INTDP Instruction
358
INTDP Instruction Phases
358
INTDP Instruction Execution
358
DP Compare Instructions
359
DP Compare Instruction Phases
359
DP Compare Instruction Execution
359
ADDDP/SUBDP Instructions
360
ADDDP/SUBDP Instruction Phases
360
ADDDP/SUBDP Instruction Execution
360
MPYI Instruction
361
MPYI Instruction Phases
361
MPYI Instruction Execution
361
MPYID Instruction
362
MPYID Instruction Phases
362
MPYID Instruction Execution
362
MPYDP Instruction
363
MPYDP Instruction Phases
363
MPYDP Instruction Execution
363
MPYSPDP Instruction
364
MPYSPDP Instruction Phases
364
MPYSPDP Instruction Execution
364
MPYSP2DP Instruction
365
Functional Unit Constraints
365
MPYSP2DP Instruction Phases
365
MPYSP2DP Instruction Execution
365
S-Unit Constraints
366
Single-Cycle .S-Unit Instruction Constraints
366
DP Compare .S-Unit Instruction Constraints
367
Cycle DP .S-Unit Instruction Constraints
368
ADDSP/SUBSP .S-Unit Instruction Constraints
369
ADDDP/SUBDP .S-Unit Instruction Constraints
370
Branch .S-Unit Instruction Constraints
371
M-Unit Constraints
372
Multiply .M-Unit Instruction Constraints
372
Cycle .M-Unit Instruction Constraints
373
MPYI .M-Unit Instruction Constraints
374
MPYID .M-Unit Instruction Constraints
375
MPYDP .M-Unit Instruction Constraints
376
MPYSP .M-Unit Instruction Constraints
377
MPYSPDP .M-Unit Instruction Constraints
378
MPYSP2DP .M-Unit Instruction Constraints
379
L-Unit Constraints
380
Single-Cycle .L-Unit Instruction Constraints
380
Cycle .L-Unit Instruction Constraints
381
INTDP .L-Unit Instruction Constraints
382
ADDDP/SUBDP .L-Unit Instruction Constraints
383
D-Unit Instruction Constraints
384
Load .D-Unit Instruction Constraints
384
Store .D-Unit Instruction Constraints
385
Single-Cycle .D-Unit Instruction Constraints
386
LDDW Instruction with Long Write Instruction Constraints
387
Performance Considerations
388
Pipeline Operation with Multiple Execute Packets in a Fetch Packet
388
Pipeline Operation: Fetch Packets with Different Numbers of Execute Packets
389
Multicycle Nops
390
Multicycle NOP in an Execute Packet
390
Branching and Multicycle Nops
391
Memory Considerations
392
Pipeline Phases Used During Memory Accesses
392
Program Memory Accesses Versus Data Load Accesses
392
Program and Data Memory Stalls
393
Bank Interleaved Memory
394
Load from Memory Banks
394
Bank Interleaved Memory with Two Memory Spaces
395
Loads in Pipeline from Example 4−2
395
Interrupts
396
Overview
397
Types of Interrupts and Signals Used
397
Interrupt Priorities
398
Interrupt Service Table (IST)
401
Interrupt Service Fetch Packet
402
Interrupt Service Table with Branch to Additional Interrupt Service Code
403
Located Outside the IST
403
Interrupt Service Table
404
Summary of Interrupt Control Registers
405
Interrupt Control Registers
405
Globally Enabling and Disabling Interrupts
406
Code Sequence to Disable Maskable Interrupts Globally
407
Code Sequence to Enable Maskable Interrupts Globally
407
Individual Interrupt Control
408
Enabling and Disabling Interrupts
408
Code Sequence to Enable an Individual Interrupt (INT9)
408
Code Sequence to Disable an Individual Interrupt (INT9)
408
Status of Interrupts
409
Setting and Clearing Interrupts
409
Code to Clear an Individual Interrupt (INT6) and Read the Flag Register
409
Returning from Interrupt Servicing
410
Code to Return from NMI
410
Code to Return from a Maskable Interrupt
410
Interrupt Detection and Processing
411
Setting the Nonreset Interrupt Flag
411
Conditions for Processing a Nonreset Interrupt
411
Nonreset Interrupt Detection and Processing: Pipeline Operation
412
Actions Taken During Nonreset Interrupt Processing
413
Setting the RESET Interrupt Flag
414
RESET Interrupt Detection and Processing: Pipeline Operation
414
Actions Taken During RESET Interrupt Processing
415
Performance Considerations
416
General Performance
416
Pipeline Interaction
416
Programming Considerations
417
Single Assignment Programming
417
Code Without Single Assignment: Multiple Assignment of A1
417
Nested Interrupts
418
Code Using Single Assignment
418
Assembly Interrupt Service Routine that Allows Nested Interrupts
419
Manual Interrupt Processing
420
C Interrupt Service Routine that Allows Nested Interrupts
420
Traps
421
Code Sequence to Invoke a Trap
421
Code Sequence for Trap Return
421
Instruction Compatibility between C62X, C64X, C67X, and C67X+ Dsps
422
B Mapping between Instruction and Functional Unit
428
Functional Unit to Instruction Mapping
428
Unit Instructions and Opcode Maps
434
Instructions Executing in the .D Functional Unit
434
Instructions Executing in the .D Functional Unit
435
Opcode Map Symbols and Meanings
436
Address Generator Options for Load/Store
437
32-Bit Opcode Maps
438
Or 2 Sources Instruction Format
438
Extended .D Unit 1 or 2 Sources Instruction Format
438
Load/Store Basic Operations
438
Load/Store Long-Immediate Operations
438
Unit Instructions and Opcode Maps
439
Instructions Executing in the .L Functional Unit
439
Instructions Executing in the .L Functional Unit
440
Opcode Map Symbols and Meanings
441
32-Bit Opcode Maps
442
Or 2 Sources Instruction Format
442
Or 2 Sources, Nonconditional Instruction Format
442
Unary Instruction Format
442
Unit Instructions and Opcode Maps
443
Instructions Executing in the .M Functional Unit
443
Instructions Executing in the .M Functional Unit
444
Opcode Map Symbols and Meanings
445
32-Bit Opcode Maps
446
Extended M-Unit with Compound Operations
446
Extended .M Unit 1 or 2 Sources, Nonconditional Instruction Format
446
Extended .M-Unit Unary Instruction Format
446
Unit Instructions and Opcode Maps
447
Instructions Executing in the .S Functional Unit
447
Instructions Executing in the .S Functional Unit
448
Opcode Map Symbols and Meanings
449
32-Bit Opcode Maps
450
Or 2 Sources Instruction Format
450
Extended .S Unit 1 or 2 Sources Instruction Format
450
Extended .S Unit 1 or 2 Sources, Nonconditional Instruction Format
450
Unary Instruction Format
450
Extended .S Unit Branch Conditional, Immediate Instruction Format
450
Call Unconditional, Immediate with Implied NOP 5 Instruction Format
451
Branch with NOP Constant Instruction Format
451
Branch with NOP Register Instruction Format
451
Branch Instruction Format
451
MVK Instruction Format
451
Field Operations
451
F−11 Field Operations
451
Instructions Executing with No Unit Specified
452
Instructions Executing with No Unit Specified
453
Opcode Map Symbols and Meanings
453
No Unit Specified Instructions Opcode Map Symbol Definitions
453
32-Bit Opcode Maps
454
Loop Buffer Instruction Format
454
NOP and IDLE Instruction Format
454
Emulation/Control Instruction Format
454
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