Application Guidelines; Fast Lockup - Texas Instruments OMAP5912 Reference Manual

2.1

Application Guidelines

Fast Lockup

Figure 3. Fast Lockup
PWRDN
(TEST, SEL2, SEL1, SEL0)
LOCK
Frequency (CLKOUT)
SPRU751A
Adhere to the following guidelines to get the best performance from the cell.
A fast lockup follows this control sequence (see Figure 3):
1) PWRDN must be set to 0 any time the APLL must be used.
2) PWRDN must stay at low for a minimum time.
3) The mode selection bits (TEST, SEL2, SEL1, SEL0) must be set during
the time PWRDN is low.
4) LOCK always falls to 0 when PWRDN is set to low. This may take between
several 100 ns and 1 µs.
5) When PWRDN is raised to high, and if the input clock toggles within the
specified frequency range, the APLL locks on the target frequency and the
lock signal goes to high.
6) Jitter is in specification after LOCK has gone to high.
0 MHz
Pulse width
Time for stable lock
Lock in time
Analog Phase-Locked Loop
Target frequency
Clocks 19