Dma Transfer Latency - Texas Instruments OMAP5912 Reference Manual

DSP DMA
4.19

DMA Transfer Latency

148 Direct Memory Access (DMA) Support
External memory port: A time-out counter in the external memory interface
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(EMIF) keeps track of how many cycles the external ready pin has been
sampled low. The external memory map is divided into four memory
spaces, each of which has a programmable time-out value up to 255 DSP
cycles. When the counter reaches the time-out value, the EMIF sends a
time-out signal to the DMA controller.
Peripherals port: A time-out counter in the peripheral bus controller counts
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how many cycles have passed since a request was made to access a
peripheral. When the counter reaches 127 DSP cycles, the peripheral bus
controller sends a time-out signal to the DMA controller. The default
time-out values can be changed in the TIPB CMR register.
In response to a time-out signal, the DMA controller disables the channel (EN
= 0 in DMA_CCR); activity in the channel stops after the current element
transfer. If the corresponding interrupt enable bit is set (TOUT_IE = 1 in
DMA_CICR), the DMA controller also sets the time-out status bit (TOUT = 1
in DMA_CSR) and sends the time-out signal to the CPU as an interrupt
request. The interrupt request sets the bus-error interrupt flag bit in the CPU.
The CPU can respond to the interrupt request or ignore the interrupt request.
Each element transfer in a channel contains a read access (a transfer from the
source location to the channel buffer) and a write access (a transfer from the
channel buffer to the destination location). The time to complete this activity
depends on factors such as:
The selected frequency of the CPU clock signal. This signal, as
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propagated to the DMA controller, determines the timing for all DMA
transfers.
Wait states or other extra cycles added by or resulting from an interface.
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Competition from other channels. The DMA controller divides cycles
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among all enabled channels according to their position and priority level
in the service chain (see Section 4.4, Service Chain). If fewer channels are
enabled, more cycles are allotted per channel during a given interval of
time.
Competition from the MPU access via the MPUI. If the MPUI is sharing
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internal RAM with the channels, the DMA controller allocates cycles to the
MPUI like it does to channels. If the MPUI is given exclusive access to the
internal RAM, no channels can access the internal RAM until the MPUI
access configuration is changed (see Section 4.3, MPUI Access
Configurations).
SPRU755B