Omap1612 Stacked Ddr Support - Texas Instruments OMAP5912 Reference Manual

Introduction
1.1.1

OMAP1612 Stacked DDR Support

16 Memory Interfaces
Program the SDRAM_TYPE field of the EMIFF interface SDRAM
configuration register to specify the physical configuration of the devices.
The SDRAM type selection is the first action required from the software driver,
using the SDRAM_TYPE field of the EMIF SDRAM operation register.
The SDRAM controller supports:
-
The self-refresh mode (idle), autorefresh, and other operating modes
(HPHB, LPLB, and POM0 modes)
-
MRS command and extended MRS command for:
J
DDR SDRAM and low-power SDRAM, sent via the SDRAM request
manager
J
SDR SDRAM, all burst sizes, between 1 and 32 consecutive accesses
J
DDR SDRAM, only bursts of 8
-
Two pipelined levels of request from the SDRAM request manager to
enable page interleave timing and reduce overhead cycles by the burst
interruption mechanism.
For example, the following SDR SDRAMs from Samsung are supported:
J
K4S64163LF (4M X 16)
J
K4S28163LD (8M X 16)
The SDR interface voltage support is 1.8 V (1.65 V–1.95 V), 2.75 V (2.5 V–
3.0 V), and 3.3 V (3.0 V–3.6 V).
This interface can also support Samsung mobile SDRAM with DDR capability
at both 128M bits and 256M bits.
The DDR voltage support is 1.8 V (1.65 V – 1.95 V) only.
The OMAP1612 device includes a stacked mobile DDR (dual-data-rate)
SDRAM. This device is directly connected to the EMIFF interface, and that
interface is not available for connecting external memories in the OMAP1612
device.
The OMAP1612 stacked DDR SDRAM has the following characteristics:
-
Elpida ECK2516CBCZ−10 part
-
1.8-V power supply
-
1.8-V I/O power
SPRU756A