Low-Voltage Operation At Reduced Clock Frequency - Texas Instruments OMAP5912 Reference Manual

Ultralow-Power Device
Figure 4. Behavior of LOW_PWR in RESET_MODE 0
LOW_POWER
1.8

Low-Voltage Operation at Reduced Clock Frequency

22 Power Management
At reset, the low-power feature is disabled (POWER_CTRL_REG[0] is set to
0). The LOW_PWR signal is inactive low, which indicates a nominal voltage
requirement.
ULPD state Awake...
big sleep
1.6 V
VDD
In this mode of operation, also known as dynamic voltage scaling (DVS), the
following conditions must be met:
-
POWER_CTRL_REG[4] set to 0: Disables transition to deep sleep mode
-
POWER_CTRL_REG[10] set to 1: Enables DVS
Whenever OMAP3.2 indicates to ULPD that it is prepared to go into idle, the
transition to deep sleep is prevented, and the ULPD moves into big sleep
mode. In this mode, the OMAP3.2 input clock is shut down, but the oscillator
is still active.
In this case, LOW_PWR
POWER_CTRL_REG [11].
If POWER_CTRL_REG [11] =1 (min), LOW_PWR switches to active high,
driving the external regulator in low-voltage operation.
If POWER_CTRL_REG [11] =0 (max), LOW_PWR switches to inactive low,
driving the external regulator in nominal voltage operation.
Whenever OMAP3.2 initiates a wake-up procedure, the ULPD moves back to
awake mode but
POWER_CTRL_REG [11].
In this way, when POWER_CTRL_REG [11] =1, OMAP3.2 restarts operations
at low voltage. To ramp up the operating voltage back to nominal value, a new
Deep sleep
1.1 V
ULPD setup analog cell timer2 delays deep sleep
to big sleep/awake transition while the regulator
ramps from 1.1 V to 1.6 V.
follows the
LOW_PWR keeps
Setup Big sleep...
timer awake
value programmed
the value programmed
SPRU753A
in
in