Clock Gating In Ulpd - Texas Instruments OMAP5912 Reference Manual

5.13.2

Clock Gating in ULPD

Table 13. Hardware Requests
Hardware Request
PERIPH_NREQ (internal)
WAKEUP_NREQ
(internal)
BCLKREQ
MCLKREQ
USB_MCLK_REQ
USB_DPLL_MCLK_REQ
SPRU751A
Table 13 shows clocks from the ULPD that can be gated or ungated. Clocks
can be made active if either one of the respective clock selections is high or
if there is a wake-up request. Wake-up requests can be hardware or software
and can be disabled by software. For software requests, disables, and
associated clocks, see Table 13. In addition, some software requests can be
set up in the OMAP5912 configuration module.
Clock Requested
Input clock to
OMAP3.2 DPLL
UART_MCKO
(internal)
CAM.EXCLK
Input clock to
OMAP3.2 DPLL
UART_MCKO
CAM.EXCLK
System clock on ball
Y15 (BCLK)
System clock on ball
V5 (MCLK)
System clock
48 MHz for USB
By default, USB_MCLK_REQ requests the internal interface clock. When low,
it enables the ULPD to enter deep sleep mode, as the USB is in idle mode and
USB functionality is no longer required (OTG functionality is no longer used,
the idle modes are activated, the USB host is not used, and the USB device
is not used, is unconnected, or is put in suspend after the software
acknowledgment).
By default, USB_DPLL_MCLK_REQ requests the clock for 48 MHz for the
USB core clocks. When low, it enables the ULPD to enter deep sleep mode,
OMAP5912 Clock Architecture
Event Notes
Falling edge detected ULPD state machine
on the UART2 RX transitions to awake.
UART_MCKO transitions
from 32-kHz (deep sleep
mode) to system clock.
Any unmasked ULPD state machine
interrupt from GPIO transitions to awake.
External input set
high
External input set
high
Permanent request. Interface clock to access USB
Can be disabled by register file
software.
USB cable 48-MHz USB clock. Refer to
detection/USB USB OTG integration.
resume
Clocks 51