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Flexible static memory controller (FSMC)
Table 220. 16-bit PC-Card signals and access type (continued)
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
The FSMC Bank 4 gives access to those 3 memory spaces as described in
NAND/PC Card address mapping
Wait Feature
The CompactFlash Storage or PC Card may request the FSMC to extend the length of the
access phase programmed by MEMWAITx/ATTWAITx/IOWAITx bits, asserting the nWAIT
signal after nOE/nWE or nIORD/nIOWR activation if the wait feature is enabled through the
PWAITEN bit in the FSMC_PCRx register. In order to detect the nWAIT assertion correctly,
the MEMWAITx/ATTWAITx/IOWAITx bits must be programmed as follows:
Where max_wait_assertion_time is the maximum time taken by NWAIT to go low once
nOE/nWE or nIORD/nIOWR is low.
After the de-assertion of nWAIT, the FSMC extends the WAIT phase for 4 HCLK clock
cycles.
1365/1422
0
X
X
X-X
0
0
X
X
X-X
1
0
X
X
X-X
0
0
X
X
X-X
1
0
X
X
X-X
0
0
X
X
X-X
0
0
X
X
X-X
X
0
X
X
X-X
X
xxWAITx >= 4 + max_wait_assertion_time/HCLK
Doc ID 018909 Rev 4
Space
Access Type
Read Even Byte on D7-0
Read Odd Byte on D7-0
Write Even Byte on D7-0
Write Odd Byte on D7-0
I/O space
Read Word on D15-0
Write word on D15-0
Read Odd Byte on D15-8
Write Odd Byte on D15-8
-
Table 187: Memory mapping and timing registers
RM0090
Allowed/not
Allowed
YES
YES
YES
YES
YES
YES
Not supported
Not supported
Section 32.4.2:
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