Sdio Response 1; Sdio Data Timer Register (Sdio_Dtimer); Table 133. Response Type And Sdio_Respx Registers - ST STM32F207 Series Reference Manual

Secure digital input/output interface (SDIO)
26.9.6 SDIO response 1..4 register (SDIO_RESPx)
Address offset: (0x10 + (4 × x)); x = 1..4
Reset value: 0x0000 0000
The SDIO_RESP1/2/3/4 registers contain the status of a card, which is part of the received
response.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r r
Bits 31:0 CARDSTATUSx: see
The Card Status size is 32 or 127 bits, depending on the response type.
Register
SDIO_RESP1
SDIO_RESP2
SDIO_RESP3
SDIO_RESP4
The most significant bit of the card status is received first. The SDIO_RESP3 register LSB is
always 0b.
26.9.7

SDIO data timer register (SDIO_DTIMER)

Address offset: 0x24
Reset value: 0x0000 0000
The SDIO_DTIMER register contains the data timeout period, in card bus clock periods.
A counter loads the value from the SDIO_DTIMER register, and starts decrementing when
the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0
while the DPSM is in either of these states, the timeout status flag is set.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 DATATIME: Data timeout period
Note: A data transfer must be written to the data timer register and the data length register before
being written to the data control register.
780/1381
r r r r r r
Table

Table 133. Response type and SDIO_RESPx registers

Card Status[31:0]
Unused
Unused
Unused
Data timeout period expressed in card bus clock periods.
CARDSTATUSx
r r r r r r r
133.
Short response
DATATIME
RM0033 Rev 9
9 8 7 6 5
r r r r r r r
Long response
Card Status [127:96]
Card Status [95:64]
Card Status [63:32]
Card Status [31:1]0b
9 8 7 6 5
RM0033
4 3 2 1 0
r r r r r
4 3 2 1 0