ST STM32F40 Series Reference Manual page 1286

RM0090
d)
e)
The core does not generate a separate interrupt when NAK or NYET is received by the
host functionality.
●
Bulk and control IN transactions in DMA mode
The sequence of operations is as follows:
a)
b)
c)
d)
e)
f)
g)
h)
● Interrupt OUT transactions in DMA mode
a)
b)
service these interrupts, since the core takes care of rewinding the buffer pointers
and re-initializing the Channel without application intervention.
The core automatically issues a ping token.
When the device returns an ACK, the core continues with the transfer. Optionally,
the application can utilize these interrupts, in which case the NAK or NYET
interrupt is masked by the application.
Initialize and enable the used channel (channel x) as explained in
Channel initialization.
The OTG_HS host writes an IN request to the request queue as soon as the
channel receives the grant from the arbiter (arbitration is performed in a round-
robin fashion).
The OTG_HS host starts writing the received data to the system memory as soon
as the last byte is received with no errors.
When the last packet is received, the OTG_HS host sets an internal flag to remove
any extra IN requests from the request queue.
The OTG_HS host flushes the extra requests.
The final request to disable channel x is written to the request queue. At this point,
channel 2 is internally masked for further arbitration.
The OTG_HS host generates the CHH interrupt as soon as the disable request
comes to the top of the queue.
In response to the CHH interrupt, de-allocate the channel for other transfers.
Initialize and enable channel x as explained in
The OTG_HS host starts fetching the first packet as soon the channel is enabled
and writes the OUT request along with the last DWORD fetch. In high-bandwidth
Doc ID 018909 Rev 4
USB on-the-go high-speed (OTG_HS)
Section : Channel
Section :
initialization.
1286/1422