ST STM32F40 Series Reference Manual page 1384

RM0090
Table 225. JTAG debug port data registers (continued)
IR(3:0)
1011
1000
Data register
Access port access register
Initiates an access port and allows access to an access port register.
– When transferring data IN:
Bits 34:3 = DATA[31:0] = 32-bit data to shift in for a write request
Bits 2:1 = A[3:2] = 2-bit address (sub-address AP registers).
Bit 0 = RnW= Read request (1) or write request (0).
– When transferring data OUT:
Bits 34:3 = DATA[31:0] = 32-bit data which is read following a read
APACC
request
[35 bits]
Bits 2:0 = ACK[2:0] = 3-bit Acknowledge:
010 = OK/FAULT
001 = WAIT
OTHER = reserved
There are many AP Registers (see AHB-AP) addressed as the
combination of:
– The shifted value A[3:2]
– The current value of the DP SELECT register
Abort register
ABORT
– Bits 31:1 = Reserved
[35 bits]
– Bit 0 = DAPABORT: write 1 to generate a DAP abort.
Doc ID 018909 Rev 4
Debug support (DBG)
Details
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