ST STM32F40 Series Reference Manual page 1344

Hide thumbs Also See for STM32F40 Series:

Table of Contents

Figure 419. Asynchronous wait during a write access

1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.

address phase

Doc ID 018909 Rev 4

Flexible static memory controller (FSMC)

Memory transaction

data setup phase

data driven by FSMC

Need help?

Do you have a question about the STM32F40 Series and is the answer not in the manual?