ST STM32F40 Series Reference Manual page 1355

Flexible static memory controller (FSMC)
Bits 19:16 BUSTURN: Bus turnaround phase duration
These bits are written by software to add a delay at the end of a write/read transaction. This
delay allows to match the minimum time between consecutive transactions (t
high to NEx low) and the maximum time needed by the memory to free the data bus after a
read access (tEHQZ):
(BUSTRUN + 1)HCLK period ≥ t
EXTMOD = '0'
(BUSTRUN + 2)HCLK period ≥ max (t
0000: BUSTURN phase duration = 0 HCLK clock cycle added
...
1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)
Bits 15:8 DATAST: Data-phase duration
These bits are written by software to define the duration of the data phase (refer to
Figure 405
0000 0000: Reserved
0000 0001: DATAST phase duration = 1 × HCLK clock cycles
0000 0010: DATAST phase duration = 2 × HCLK clock cycles
...
1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
For each memory type and access mode data-phase duration, please refer to the respective
figure
Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK
clock cycles.
Note: In synchronous accesses, this value is don't care.
Bits 7:4 ADDHLD: Address-hold phase duration
These bits are written by software to define the duration of the address hold phase (refer to
Figure 414
0000: Reserved
0001: ADDHLD phase duration =1 × HCLK clock cycle
0010: ADDHLD phase duration = 2 × HCLK clock cycle
...
1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
For each access mode address-hold phase duration, please refer to the respective figure
(Figure 414
Note: In synchronous accesses, this value is not used, the address hold phase is always 1
Bits 3:0 ADDSET: Address setup phase duration
These bits are written by software to define the duration of the address setup phase (refer to
Figure 405
0000: ADDSET phase duration = 0 × HCLK clock cycle
...
1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset)
For each access mode address setup phase duration, please refer to the respective figure
(refer to
Note: In synchronous accesses, this value is don't care.
Note: PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these
memories issue the NWAIT signal during the whole latency phase to prolong the latency as
needed.
With PSRAMs (CRAMs) the filed DATLAT must be set to 0, so that the FSMC exits its
latency phase soon and starts sampling NWAIT from memory, then starts to read or write
1355/1422
to Figure 417), used in SRAMs, ROMs and asynchronous NOR Flash accesses:
(Figure 405 to Figure 417).
to Figure 417), used in mode D and multiplexed accesses:
to Figure 417).
memory clock period duration.
to Figure 417), used in SRAMs, ROMs and asynchronous NOR Flash accesses:
Figure 405 to Figure
Doc ID 018909 Rev 4
and (BUSTRUN + 2)HCLK period ≥ t
EHELmin
, t
EHELmin EHQZmax
417).
EHEL
EHQZmax
) if EXTMOD = '1'.
RM0090
from NEx
if