ST STM32F40 Series Reference Manual page 1298

RM0090
6. The OUT data transfer completed pattern for an OUT endpoint is written to the receive
FIFO on one of the following conditions:
–
–
7. When either the application pops this entry (OUT data transfer completed), a transfer
completed interrupt is generated for the endpoint and the endpoint enable is cleared.
Application programming sequence:
1. Program the OTG_HS_DOEPTSIZx register for the transfer size and the corresponding
packet count.
2. Program the OTG_HS_DOEPCTLx register with the endpoint characteristics, and set
the EPENA and CNAK bits.
–
–
3. Wait for the RXFLVL interrupt (in OTG_HS_GINTSTS) and empty the data packets
from the receive FIFO.
–
4. Asserting the XFRC interrupt (OTG_HS_DOEPINTx) marks a successful completion of
the nonisochronous OUT data transfer.
5. Read the OTG_HS_DOEPTSIZx register to determine the size of the received data
payload.
●
Generic isochronous OUT data transfer
This section describes a regular isochronous OUT data transfer.
Application requirements:
1. All the application requirements for nonisochronous OUT data transfers also apply to
isochronous OUT data transfers.
2. For isochronous OUT data transfers, the transfer size and packet count fields must
always be set to the number of maximum-packet-size packets that can be received in a
single frame and no more. Isochronous OUT data transfers cannot span more than 1
frame.
3. The application must read all isochronous OUT data packets from the receive FIFO
(data and status) before the end of the periodic frame (EOPF interrupt in
OTG_HS_GINTSTS).
4. To receive data in the following frame, an isochronous OUT endpoint must be enabled
after the EOPF (OTG_HS_GINTSTS) and before the SOF (OTG_HS_GINTSTS).
Internal data flow:
1. The internal data flow for isochronous OUT endpoints is the same as that for
nonisochronous OUT endpoints, but for a few differences.
2. When an isochronous OUT endpoint is enabled by setting the Endpoint Enable and
clearing the NAK bits, the Even/Odd frame bit must also be set appropriately. The core
receives data on an isochronous OUT endpoint in a particular frame only if the
following condition is met:
–
3. When the application completely reads an isochronous OUT data packet (data and
status) from the receive FIFO, the core updates the RXDPID field in
The transfer size is 0 and the packet count is 0
The last OUT data packet written to the receive FIFO is a short packet
(0 ≤ packet size < maximum packet size)
EPENA = 1 in OTG_HS_DOEPCTLx
CNAK = 1 in OTG_HS_DOEPCTLx
This step can be repeated many times, depending on the transfer size.
EONUM (in OTG_HS_DOEPCTLx) = SOFFN[0] (in OTG_HS_DSTS)
Doc ID 018909 Rev 4
USB on-the-go high-speed (OTG_HS)
1298/1422