C Data Register (I2C_Dr); C Status Register 1 (I2C_Sr1) - ST STM32F100 Series Reference Manual

RM0041
2
22.6.5 I

C Data register (I2C_DR)

Address offset: 0x10
Reset value: 0x0000
15 14 13 12
Reserved
Bits 15:8 Reserved, must be kept at reset value
Bits 7:0 DR[7:0] 8-bit data register
– Transmitter mode: Byte transmission starts automatically when a byte is written in the DR
– Receiver mode: Received byte is copied into DR (RxNE=1). A continuous transmit stream
Note: In slave mode, the address is not copied into DR.
2
22.6.6 I

C Status register 1 (I2C_SR1)

Address offset: 0x14
Reset value: 0x0000
15 14 13 12
SMB TIME PEC
ALERT OUT ERR
Res.
rc_w0 rc_w0 rc_w0
Bit 15 SMBALERT: SMBus alert
– Cleared by software writing 0, or by hardware when PE=0.
11 10 9
Byte received or to be transmitted to the bus.
register. A continuous transmit stream can be maintained if the next data to be transmitted is
put in DR once the transmission is started (TxE=1)
can be maintained if DR is read before the next data byte is received (RxNE=1).
Write collision is not managed (DR can be written if TxE=0).
If an ARLO event occurs on ACK pulse, the received byte is not copied into DR and so
cannot be read.
11 10 9
OVR AF ARLO
rc_w0 rc_w0 rc_w0
In SMBus host mode:
0: no SMBALERT
1: SMBALERT event occurred on pin
In SMBus slave mode:
0: no SMBALERT response address header
1: SMBALERT response address header to SMBALERT LOW received
Inter-integrated circuit (I2C) interface
8 7 6
rw rw rw
8 7 6
BERR TxE RxNE
Res.
rc_w0 r r
RM0041 Rev 6
5 4 3 2
DR[7:0]
rw rw rw
5 4 3 2
STOPF ADD10 BTF
r r r
1 0
rw rw
1 0
ADDR SB
r r
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