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Note that care should be taken in asynchronous mode whenever the framesync clock (FSR, FST) is not sourced directly from its associated
bit clock (SCKR,SCKT). Proper phase relationships must be maintained between these clocks in order to guarantee proper operation of the
ESAI.
The TCCR control bits are described in the following paragraphs.
8.3.1.1
TCCR Transmit Prescale Modulus Select (TPM7–TPM0) - Bits 7–0
The TPM7–TPM0 bits specify the divide ratio of the prescale divider in the ESAI transmitter clock generator. A divide ratio from 1 to 256
(TPM[7:0]=$00 to $FF) may be selected. The bit clock output is available at the transmit serial bit clock (SCKT) pin of the DSP. The bit clock
output is also available internally for use as the bit clock to shift the transmit and receive shift registers. The ESAI transmit clock generator
functional diagram is shown in
Figure
ERI0=1
EXTAL
F
OSC
ERI0=0
HCKR
RHCKD
SCKR
RCKD
SCKT
TCKD
THCKD
HCKT
ETI0=1
EXTAL
F
OSC
ETI0=0
Notes:
1.ETIx, ETOx, ERIx and EROx bit descriptions are covered in
2. Fosc is the DSP56300 Core internal clock frequency.
Figure 8-3. ESAI Clock Generator Functional Block Diagram
Freescale Semiconductor
8-3.
RHCKD=1
PRESCALE
DIVIDE BY 1
DIVIDE
BY 2
DIVIDE BY 8
RHCKD=0
ERO0=1
EXTAL
ERO0=0
FLAG0 OUT
FLAG0 IN
(SYNC MODE)
(SYNC MODE)
SYN=1
SYN=0
INTERNAL BIT CLOCK
ETO0=0
EXTAL
ETO0=1
THCKD=0
PRESCALE
DIVIDE BY 1
DIVIDE
BY 2
DIVIDE BY 8
THCKD=1
DSP56374 Users Guide, Rev. 1.2
DIVIDER
DIVIDE BY 1
OR
TO DIVIDE BY
256
RPSR
RPM0 - RPM7
INTERNAL BIT CLOCK
RSWS4-RSWS0
RX WORD
LENGTH DIVIDER
SYN=0
RX SHIFT REGISTER
RCLOCK
TSWS4-TSWS0
SYN=1
TCLOCK
TX WORD
LENGTH DIVIDER
TX SHIFT REGISTER
TPSR
TPM0 - TPM7
DIVIDER
DIVIDE BY 1
OR
TO DIVIDE BY
256
Section 6.2.2.4, ESAI/EXTAL Clocking Control
ESAI Programming Model
DIVIDER
DIVIDE BY 1
TO DIVIDE BY
16
RFP0 - RFP3
RX WORD
CLOCK
TX WORD
CLOCK
TFP0 - TFP3
DIVIDER
DIVIDE BY 1
TO DIVIDE BY
16
8-7
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