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Overview
1.9
DMA Controller
The DMA controller enables data movement and rearrangement while the DSP cores work
independently. The DMA controller transfers blocks of data to and from the M2 memory, M3
memory, and the DDR SDRAM controller. It has 16 high-speed bidirectional channels and can
be commanded from each of the DSP subsystems, as well as from an off-device initiator through
the RapidIO or PCI using BDs. All channels are capable of complex data movement and
advanced transaction chaining. Operations such as descriptor fetches and block transfers are
initiated by each of the sixteen channels. Full duplex operation allows the DMA controller to read
data from one target and store it in its internal memory while concurrently writing another buffer
to another a target. This capability can be used extensively when data is read from the M3
memory and written into the M2 memory. The bidirectional DMA controller reads from one of
the CLASS target ports while writing to the second one. The DMA controller supports smart
arbitration algorithms such as round robin, bandwidth control, and a timer-based mechanism
using an earliest deadline first (EDF) algorithm.
1.10
TDM
The TDM interface connects gluelessly to common telecommunication framers, such as T1 and
E1. It can interface with multiple buses, such as H-MVIP/H.110 devices, TSI, and codecs such as
AC-97. It provides a total 4096 channels that are timing compliant with their clock, sync and data
signals. The TDM is composed of eight identical and independent modules. Each TDM module
can be configured in one of the following modes:
Independent receive and transmit mode. The transmitter has an input clock, output data
and a frame sync that can be configured as either input or output. There are up to 256
transmit channels and up to 256 receive channels. The receiver has an input clock, input
data, and an input frame sync.
Shared sync and clock mode. Two receive and two transmit links share the same clock and
the frame sync: The sync can be configured as either input or output. Each of the two
transmit and receive links supports up to 128 channels.
Shared data link mode. Up to four full-duplex data links, which operate as either transmit
or receive, have the same clock and frame sync. Each link supports up to 128 channels.
If all are used, the TDM modules can support up to 500 Mbps with a clock frequency up to 62.5
MHz (62.5 Mbps × 8 TDMs). Each channel can be 2, 4, 8, or 16 bits wide. All the channels share
the same width during the TDM operation. When the slot size is 8 bits wide, the selected
channels can be defined as A-law/µ-law. These channels are converted to 13/14 bits, which are
padded into 16 bits and stored in memory. Each receive and transmit channel can be active or not.
An active channel has a configurable buffer located in either in M2, M3, or DDR memory. The
TDMs support either 0.5 ms (4 frames) or 1 ms (8 frames) latency. The buffers of one TDM
interface are the same size and are filled/emptied at the same rate. A-law/u-law buffers are filled
1-20
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor
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