Table 3-8 Interpreting Page Table Entry Bits [1:0] - ARM ARM926EJ-S Technical Reference Manual

Memory Management Unit
3.2.9 Translating large page references
3-16
Bits
Large Small Tiny
[11:4] [11:4] [5:4]
[3:2] [3:2] [3:2]
[1:0] [1:0] [1:0]
The two least significant bits of the second-level descriptor indicate the descriptor type
as shown in Table 3-8.
Value Meaning
0 0 Invalid
0 1 Large page
1 0 Small page
1 1 Tiny page
Note
Tiny pages do not support subpage permissions and therefore only have one set of
access permission bits.
Figure 3-10 on page 3-17 shows the complete translation sequence for a 64KB large
page.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Table 3-7 Second-level descriptor bits (continued)
Description
Access permission bits. Domain access control on page 3-24
and Fault checking sequence on page 3-26 show how to
interpret the access permission bits.
These bits, C and B, indicate whether the area of memory
mapped by this page is treated as write-back cachable,
write-through cachable, noncached buffered, or noncached
nonbuffered.
These bits indicate the page size and validity and are
interpreted as shown in Table 3-8.

Table 3-8 Interpreting page table entry bits [1:0]

Description
Generates a page translation fault
Indicates that this is a 64KB page
Indicates that this is a 4KB page
Indicates that this is a 1KB page
ARM DDI0198D