Tcm And Cache Access Priorities; Table 4-5 Instruction Access Priorities To The Tcm And Cache; Table 4-6 Data Access Priorities To The Tcm And Cache - ARM ARM926EJ-S Technical Reference Manual

Caches and Write Buffer
4.4

TCM and cache access priorities

4-8
The priorities that apply to the ARM926EJ-S processor for instruction accesses are
shown in Table 4-5. The ARM926EJ-S processor gives highest priority to an address
that is in the instruction TCM region.

Table 4-5 Instruction access priorities to the TCM and cache

Address in
ITCM region
Yes
Yes
Yes
No
No
The priorities that apply to the ARM926EJ-S processor for data accesses are shown in
Table 4-6. The Harvard arrangement for the TCM and caches requires that data reads
and writes can access the Instruction TCM for both reads and writes. (The column order
for Table 4-6 is deliberately the same as for instruction accesses in Table 4-5.)
Address in
ITCM Region
Yes
No
No
Yes
Yes
No
No
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Address in Cachable in
DTCM region page descriptor
Yes Don't care
No Cachable
No Noncachable
Don't care Cachable
Don't care Noncachable

Table 4-6 Data access priorities to the TCM and cache

Address in Cachable in
DTCM region page descriptor
Yes Don't care
Yes Cachable
Yes Noncachable
No Cachable
No Noncachable
No Cachable
No Noncachable
ARM926EJ-S
behavior
Access ITCM
Access ITCM
Access ITCM
Access ICache
Access external memory
ARM926EJ-S
behavior
Access DTCM
Access DTCM
Access DTCM
Access ITCM
Access ITCM
Access DCache
Access external memory
ARM DDI0198D