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7.5
Explanation of Operation of 16-bit Free-run Timer
After a reset, the 16-bit free-run timer starts incrementing from "0000
counter value is incremented from "FFFF
I Setting of 16-bit Free-run Timer
Operation of the 16-bit free-run timer requires the setting shown in Figure 7.5-1
TCCS
TCDT
: Using bit
0
: Setting to "0"
Reserved
: Be sure to set to "0".
I Operation of 16-bit Free-run Timer
• After a reset, the 16-bit free-run timer starts incrementing from "0000
count clock selected by the count clock select bits (TCCS: CLK2, CLK1, CLK0).
• When the counter value of the timer counter data register (TCDT) is incremented from "FFFF
"0000
set to 1 and the 16-bit free-run timer starts incrementing again from "0000
• When an overflow occurs (TCCS: IVF = 1) with an overflow interrupt enabled (TCCS: IVFE = 1), an
overflow interrupt request is generated.
• When stopping the count operation of the timer counter data register (TCDT), write "1" to the timer
count operation bit (TCCS: STOP).
• Set the counter value in the timer counter data register (TCDT) after stopping the count operation of the
16-bit free-run timer.After completing setting of the count value, enable the count operation of the 16-
bit free-run timer (TCCS: STOP = 0).
Figure 7.5-1 Setting of 16-bit Free-run Timer
bit15 14
13
12
11
Counter value of 16-bit free-run timer
", an overflow occurs.When an overflow occurs, the overflow generation flag bit (TCCS: IVF) is
H
" to "0000
", an overflow occurs.
H
H
10
9
bit8 bit7
6
IVF IVFE STOP
0
CHAPTER 7 16-bit I/O timer
".When the
H
5
4
3
2
1
bit0
Re-
CLR
CLK2
CLK1 CLK0
served
0
0
" in synchronization with the
H
".
H
"to
H
237
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