Operation Of 16-Bit Free-Running Timer - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 12 16-BIT INPUT/OUTPUT TIMER

12.3.1 Operation of 16-bit free-running timer

This section explains the operation and timing of the 16-bit free-running timer.
I Operation of 16-bit free-running timer
The 16-bit free-running timer starts counting at a counter value of "0000" after a reset operation
is cleared. This counter value is used as a reference time for 16-bit output compare and 16-bit
input capture.
The count value is cleared by a clear operation under the following conditions:
• Overflow occurs
• Compare match is found with the output compare value 0 (mode setting is required)
• TCCS register CLR bit is set to "1" during operation
• TCDC register is set to "0000" during operation
• Reset occurs
An interrupt occurs if an overflow is generated or if the value of compare register 0 matches
compare results, causing clearing of the count value (a compare results match interrupt requires
mode setting)
Figure 12.3-1 "Timing chart of counter cleared because of overflow" shows the timing chart of
the counter cleared because of an overflow. Figure 12.3-2 "Timing chart of counter cleared
because of compare results match" shows the timing chart of the counter cleared because of a
compare results match.
Figure 12.3-1 Timing chart of counter cleared because of overflow
Counter value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Reset
Interrupt
240
Time