Detailed Explanation Of Registers For 16-Bit Free-Run Timer - Fujitsu MB90420/5 (A) Series Hardware Manual

11.3.2 Detailed Explanation of Registers for 16-bit Free-run Timer

The 16-bit free-run timer has the following three registers:
• Data register (TCDT)
• Compare clear register (CPCLR)
• Timer control status register (TCCS)
n Data register (TCDT)
Timer data register (upper)
Address: 000027
H
Timer data register (lower)
Address: 000026
H
This register can read the count value of the 16-bit free-run timer. The value of the counter is cleared to
0000 at reset. The value of the timer can be set by writing to this register but must be set in the stop state
(STOP = 1). Perform word access to this register. The 16-bit free-run timer is initialized by the following
factors.
• Initialization by reset
– Initialization by clearing the control status register
– Initialization by matching
n Compare clear register (CPCLR)
Compare clear register (upper)
Address: 000025
H
Compare clear register (lower)
Address: 000024
H
This is the 16-bit length compare register which compares with the value of the 16-bit free-run timer. The
initial value of this register is undefined, so set the value before enabling the operation. Perform word
access to this register. When this register value and the 16-bit free-running timer value match, the the latter
is initialized to 0000 and the compare clear interrupt flag is set. Also, an interrupt request is issued to the
CPU when interrupts are enabled.
INPUT CAPTURE
bit 15 bit 14 bit 13
T15 T14 T13
(R/W) (R/W) (R/W)
(0) (0) (0)
bit 7 bit 6 bit 5
T07 T06 T05
(R/W) (R/W) (R/W)
(0) (0) (0)
bit 15 bit 14 bit 13
CL15 CL14 CL13
(R/W) (R/W) (R/W)
(X) (X) (X)
bit 7 bit 6 bit 5
CL07 CL06 CL05
(R/W) (R/W) (R/W)
(X) (X) (X)
bit 12 bit 11 bit 10
T12 T11 T10
(R/W) (R/W) (R/W)
(0) (0) (0)
bit 4 bit 3 bit 2
T04 T03 T02
(R/W) (R/W) (R/W)
(0) (0) (0)
bit 12 bit 11 bit 10
CL12 CL11 CL10
(R/W) (R/W) (R/W)
(X) (X) (X)
bit 4 bit 3 bit 2
CL04 CL03 CL02
(R/W) (R/W) (R/W)
(X) (X) (X)
11-9
bit 9 bit 8
T09 T08 TCDT
(R/W) (R/W)
← Read/write
(0) (0)
← Initial value
bit 1 bit 0
T01 T00 TCDT
(R/W) (R/W) ← Read/write
(0) (0) ← Initial value
bit 9 bit 8
CL09 CL08 CPCLR
(R/W) (R/W)
← Read/write
(X) (X)
← Initial value
bit 1 bit 0
CL01 CL00 CPCLR
(R/W) (R/W)
← Read/write
(X) (X) ← Initial value