Power Control/Status Register (Pwr_Csr) - ST STM32F100 Series Reference Manual

Power control (PWR)
4.4.2

Power control/status register (PWR_CSR)

Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.
31 30 29
15 14 13
Reserved
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 EWUP: Enable WKUP pin
This bit is set and cleared by software.
0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup
the device from Standby mode.
1: WKUP pin is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP pin wakes-up the system from Standby mode).
Note: This bit is reset by a system Reset.
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 PVDO: PVD output
This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.
0: V
1: V
Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after
Bit 1 SBF: Standby flag
This bit is set by hardware and cleared only by a POR/PDR (power on reset/power down reset)
or by setting the CSBF bit in the
0: Device has not been in Standby mode
1: Device has been in Standby mode
Bit 0 WUF: Wakeup flag
This bit is set by hardware and cleared by hardware, by a system reset or by setting the
CWUF bit in the
0: No wakeup event occurred
1: A wakeup event was received from the WKUP pin or from the RTC alarm
Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the
62/709
28 27 26 25
12 11 10 9
/V is higher than the PVD threshold selected with the PLS[2:0] bits.
DD DDA
/V is lower than the PVD threshold selected with the PLS[2:0] bits.
DD DDA
Standby or reset until the PVDE bit is set.
Power control register (PWR_CR)
EWUP bit) when the WKUP pin level is already high.
24 23 22
Reserved
8 7 6
EWUP
Reserved
rw
Power control register (PWR_CR)
RM0041 Rev 6
21 20 19 18
5 4 3 2
PVDO
r
RM0041
17 16
1 0
SBF WUF
r r