Pwr Power Control/Status Register (Pwr_Csr) - ST STM32F207 Series Reference Manual

RM0033
Bit 3 CSBF: Clear standby flag
This bit is always read as 0.
0: No effect
1: Clear the SBF Standby Flag (write).
Bit 2 CWUF: Clear wakeup flag
This bit is always read as 0.
0: No effect
1: Clear the WUF Wakeup Flag after 2 System clock cycles
Bit 1 PDDS: Power down deepsleep
This bit is set and cleared by software. It works together with the LPDS bit.
0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the
LPDS bit.
1: Enter Standby mode when the CPU enters deepsleep.
Bit 0 LPDS: Low-power deep sleep
This bit is set and cleared by software. It works together with the PDDS bit.
0: Voltage regulator on during Stop mode
1: Voltage regulator in low-power mode during Stop mode
4.4.2

PWR power control/status register (PWR_CSR)

Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.
31 30 29
15 14 13
Reserved
Res.
Bits 31:10 Reserved, always read as 0.
Bit 9 BRE: Backup regulator enable
When set, the Backup regulator (used to maintain backup SRAM content in Standby and V
modes) is enabled. If BRE is reset, the backup regulator is switched off. The backup SRAM
can still be used but its content will be lost in the Standby and V
application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that the
data written into the RAM will be maintained in the Standby and V
0: Backup regulator disabled
1: Backup regulator enabled
Note: This bit is not reset when the device wakes up from Standby mode, by a system reset,
28 27 26 25
12 11 10 9
BRE
rw
or by a power reset.
24 23 22
Reserved
Res.
8 7 6
EWUP
Reserved
Res.
rw
RM0033 Rev 9
Power control (PWR)
21 20 19 18
5 4 3 2
BRR PVDO
r r
modes. Once set, the
BAT
modes.
BAT
17 16
1 0
SBF WUF
r r
BAT
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