Spi Control Register 2 (Spi_Cr2) - ST STM32F205 series Reference Manual

Serial peripheral interface (SPI)
Bit 2 MSTR: Master selection
Note: This bit should not be changed when communication is ongoing.
Bit1 CPOL: Clock polarity
Note: This bit should not be changed when communication is ongoing.
Bit 0 CPHA: Clock phase
Note: This bit should not be changed when communication is ongoing.
25.5.2

SPI control register 2 (SPI_CR2)

Address offset: 0x04
Reset value: 0x0000
15 14 13 12
Reserved
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 TXEIE: Tx buffer empty interrupt enable
Bit 6 RXNEIE: RX buffer not empty interrupt enable
Bit 5 ERRIE: Error interrupt enable
Bit 4 FRF: Frame format
Note: This bit is not used in I
Bit 3 Reserved. Forced to 0 by hardware.
728/1378
0: Slave configuration
1: Master configuration
2
It is not used in I S mode.
0: CK to 0 when idle
1: CK to 1 when idle
2
It is not used in I S mode and SPI TI mode.
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
2
It is not used in I S mode and SPI TI mode.
11 10 9
0: TXE interrupt masked
1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set.
0: RXNE interrupt masked
1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is
set.
This bit controls the generation of an interrupt when an error condition occurs UDR, OVR in
2
I S mode)(CRCERR, OVR, MODF in SPI mode, FRE in TI mode and UDR, OVR, and FRE
2
in I S mode).
0: Error interrupt is masked
1: Error interrupt is enabled
0: SPI Motorola mode
1 SPI TI mode
8 7 6 5
TXEIE RXNEIE ERRIE
rw rw rw
2
S mode.
RM0033 Rev 8
4 3 2 1
FRF SSOE TXDMAEN RXDMAEN
Res.
rw rw rw
RM0033
0
rw