Spi Control Register 2 (Spi_Cr2) - ST STM32F100 Series Reference Manual

Serial peripheral interface (SPI)
Bit 8 SSI: Internal slave select
Bit 7 LSBFIRST: Frame format
Note: This bit should not be changed when communication is ongoing.
Bit 6 SPE: SPI enable
Note: When disabling the SPI, follow the procedure described in
Bits 5:3 BR[2:0]: Baud rate control
Note: These bits should not be changed when communication is ongoing.
Bit 2 MSTR: Master selection
Note: This bit should not be changed when communication is ongoing.
Bit1 CPOL: Clock polarity
Note: This bit should not be changed when communication is ongoing.
Bit 0 CPHA: Clock phase
Note: This bit should not be changed when communication is ongoing.
21.4.2

SPI control register 2 (SPI_CR2)

Address offset: 0x04
Reset value: 0x0000
15 14 13 12
Reserved
560/709
This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the
NSS pin and the IO value of the NSS pin is ignored.
0: MSB transmitted first
1: LSB transmitted first
0: Peripheral disabled
1: Peripheral enabled
SPI.
000: f /2
PCLK
001: f /4
PCLK
010: f /8
PCLK
011: f /16
PCLK
100: f /32
PCLK
101: f /64
PCLK
110: f /128
PCLK
111: f /256
PCLK
0: Slave configuration
1: Master configuration
0: CK to 0 when idle
1: CK to 1 when idle
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
11 10 9 8 7 6 5
TXEIE RXNEIE ERRIE
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RM0041 Rev 6
Section 21.3.8: Disabling the
4 3 2 1
Res. Res. SSOE TXDMAEN RXDMAEN
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RM0041
0
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