External Memory Interface Signals; Table 49. Non-Multiplexed I/O Nor Flash Memory; Table 50. 16-Bit Multiplexed I/O Nor Flash Memory - ST STM32F446 Series Reference Manual

Flexible memory controller (FMC)
11.5.1

External memory interface signals

Table 49,
Flash memory, SRAM and PSRAM.
Note: The prefix "N" identifies the signals that are active low.
NOR Flash memory, non-multiplexed I/Os
The maximum capacity is 512 Mbits (26 address lines).
NOR Flash memory, 16-bit multiplexed I/Os
FMC signal name
CLK
A[25:16]
AD[15:0]
NE[x]
NOE
NWE
NL(=NADV)
NWAIT
The maximum capacity is 512 Mbits.
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Table 50 and Table 51

Table 49. Non-multiplexed I/O NOR Flash memory

FMC signal name
CLK
A[25:0]
D[15:0]
NE[x]
NOE
NWE
NL(=NADV)
NWAIT

Table 50. 16-bit multiplexed I/O NOR Flash memory

I/O
O
O
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
I/O
O
O
O
Latch enable (this signal is called address valid, NADV, by some NOR
O
I
list the signals that are typically used to interface with NOR
I/O
O
O
I/O
O
O
O
Latch enable (this signal is called address
O
valid, NADV, by some NOR Flash devices)
I NOR Flash wait input signal to the FMC
Clock (for synchronous access)
Address bus
A[15:0] and data D[15:0] are multiplexed on the databus)
Chip Select, x = 1..4
Output enable
Write enable
Flash devices)
NOR Flash wait input signal to the FMC
RM0390 Rev 4
Function
Clock (for synchronous access)
Address bus
Bidirectional data bus
Chip Select, x = 1..4
Output enable
Write enable
Function
RM0390