External Memory Interface Signals; Table 44. Programmable Nor/Psram Access Parameters - ST STM32F423 Reference Manual

RM0430
and synchronous accesses depending on the CCKEN bit configuration in the FSMC_BCR1
register:
•
If the CCLKEN bit is reset, the FSMC generates the clock (CLK) only during
synchronous accesses (Read/write transactions).
• If the CCLKEN bit is set, the FSMC generates a continuous clock during asynchronous
and synchronous accesses. To generate the FSMC_CLK continuous clock, Bank 1
must be configured in Synchronous mode (see
registers). Since the same clock is used for all synchronous memories, when a
continuous output clock is generated and synchronous accesses are performed, the
AHB data size has to be the same as the memory data width (MWID) otherwise the
FSMC_CLK frequency will be changed depending on AHB data transaction (refer to
Section 11.5.5: Synchronous transactions
The size of each bank is fixed and equal to 64 Mbytes. Each bank is configured through
dedicated registers (see
The programmable memory parameters include access times (see
for wait management (for PSRAM and NOR Flash accessed in Burst mode).
Parameter
Address
setup
Address hold
Data setup
Bust turn
Clock divide
ratio
Data latency
11.5.1

External memory interface signals

Table 45,
Flash memory, SRAM and PSRAM.
Note: The prefix "N" identifies the signals that are active low.
Section 11.5.6: NOR/PSRAM controller

Table 44. Programmable NOR/PSRAM access parameters

Function
Duration of the address
setup phase
Duration of the address hold
phase
Duration of the data setup
phase
Duration of the bus
turnaround phase
Number of AHB clock cycles
(HCLK) to build one memory
clock cycle (CLK)
Number of clock cycles to
issue to the memory before
the first data of the burst
Table 46 and Table 47
Flexible static memory controller (FSMC)
Section 11.5.6: NOR/PSRAM controller
for FSMC_CLK divider ratio formula).
Access mode
Asynchronous
Asynchronous,
muxed I/Os
Asynchronous
Asynchronous and
synchronous read
/ write
Synchronous
Synchronous
list the signals that are typically used to interface with NOR
RM0430 Rev 8
registers).
Table 44) and support
Unit Min.
AHB clock cycle
0
(HCLK)
AHB clock cycle
1
(HCLK)
AHB clock cycle
1
(HCLK)
AHB clock cycle
0
(HCLK)
AHB clock cycle
2
(HCLK)
Memory clock
2
cycle (CLK)
Max.
15
15
256
15
16
17
269/1324
306