External Memory Interface Signals; Table 93. Nonmultiplexed I/O Nor Flash; Table 94. Multiplexed I/O Nor Flash - ST STM32F100 Series Reference Manual

RM0041
Parameter
Clock divide
ratio
Data latency
20.5.1

External memory interface signals

Table 93,
flash, SRAM and PSRAM.
Note: Prefix "N". specifies the associated signal as active low.
NOR flash, nonmultiplexed I/Os
CLK
A[25:0]
D[15:0]
NE[x]
NOE
NWE
NL(=NADV)
NWAIT
NOR flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26
address lines).
NOR flash, multiplexed I/Os
FSMC signal name
CLK
A[25:16]
AD[15:0]
NE[x]
NOE
NWE
Table 92. Programmable NOR/PSRAM access parameters (continued)
Function
Number of AHB clock cycles
(HCLK) to build one memory
clock cycle (CLK)
Number of clock cycles to
issue to the memory before
the first data of the burst
Table 94 and Table 95

Table 93. Nonmultiplexed I/O NOR flash

FSMC signal name

Table 94. Multiplexed I/O NOR flash

I/O
O Clock (for synchronous access)
O Address bus
I/O 16-bit multiplexed, bidirectional address/data bus
O Chip select, x = 1..4
O Output enable
O Write enable
Flexible static memory controller (FSMC)
Access mode
Synchronous
Synchronous
list the signals that are typically used to interface NOR
I/O
O Clock (for synchronous access)
O Address bus
I/O Bidirectional data bus
O Chip select, x = 1..4
O Output enable
O Write enable
Latch enable (this signal is called address
O
valid, NADV, by some NOR flash devices)
I NOR flash wait input signal to the FSMC
RM0041 Rev 6
Unit
AHB clock cycle
(HCLK)
Memory clock
cycle (CLK)
Function
Function
Min. Max.
2 16
2 17
499/709
535