External Memory Interface Signals; Table 173. Programmable Nor/Psram Access Parameters; Table 174. Nonmultiplexed I/O Nor Flash - ST STM32F207 Series Reference Manual

RM0033
For synchronous accesses, the FSMC issues the clock (CLK) to the selected external
device only during the read/write transactions. This clock is a submultiple of the HCLK clock.
The size of each bank is fixed and equal to 64 Mbytes.
Each bank is configured by means of dedicated registers (see
The programmable memory parameters include access timings (see
for wait management (for PSRAM and NOR Flash accessed in burst mode).
Parameter
Address
setup
Address hold
Data setup
Bus turn
Clock divide
ratio
Data latency
31.5.1

External memory interface signals

Table 174,
Flash, SRAM and PSRAM.
Note: Prefix "N". specifies the associated signal as active low.
NOR Flash, nonmultiplexed I/Os
CLK
A[25:0]
D[15:0]
NE[x]
NOE
NWE
NL(=NADV)
NWAIT

Table 173. Programmable NOR/PSRAM access parameters

Function
Duration of the address
setup phase
Duration of the address hold
phase
Duration of the data setup
phase
Duration of the bus
turnaround phase
Number of AHB clock cycles
(HCLK) to build one memory
clock cycle (CLK)
Number of clock cycles to
issue to the memory before
the first data of the burst
Table 175 and Table 176

Table 174. Nonmultiplexed I/O NOR Flash

FSMC signal name
Flexible static memory controller (FSMC)
Access mode
Asynchronous
Asynchronous,
muxed I/Os
Asynchronous
Asynchronous and
synchronous
read/write
Synchronous
Synchronous
list the signals that are typically used to interface NOR
I/O
O Clock (for synchronous access)
O Address bus
I/O Bidirectional data bus
O Chip select, x = 1..4
O Output enable
O Write enable
Latch enable (this signal is called address
O
valid, NADV, by some NOR Flash devices)
I NOR Flash wait input signal to the FSMC
RM0033 Rev 9
Section 31.5.6).
Table 173) and support
Unit Min.
AHB clock cycle
0
(HCLK)
AHB clock cycle
1
(HCLK)
AHB clock cycle
1
(HCLK)
AHB clock cycle
0
(HCLK)
AHB clock cycle
2
(HCLK)
Memory clock
2
cycle (CLK)
Function
1267/1381
Max.
15
15
256
15
16
17
1318