Hardware Watchdog; Register Access Protection; Debug Mode; Table 86. Min/Max Iwdg Timeout Period (In Ms) At 40 Khz (Lsi) - ST STM32F100 Series Reference Manual

Independent watchdog (IWDG)
18.3.1

Hardware watchdog

If the "Hardware watchdog" feature is enabled through the device option bits, the watchdog
is automatically enabled at power-on, and generates a reset unless the Key register is
written by the software before the counter reaches end of count.
18.3.2

Register access protection

Write access to the IWDG_PR and IWDG_RLR registers is protected. To modify them, first
write the code 0x5555 in the IWDG_KR register. A write access to this register with a
different value breaks the sequence and register access is protected again. This implies that
it is the case of the reload operation (writing 0xAAAA).
A status register is available to indicate that an update of the prescaler or the down-counter
reload value is on going.
18.3.3

Debug mode

When the microcontroller enters debug mode (Cortex
either continues to work normally or stops, depending on DBG_IWDG_STOP configuration
bit in DBG module. For more details, refer to
watchdog and I
CORE
LSI
(40 kHz)
VDD voltage domain
Note: The watchdog function is implemented in the V
Standby modes.
Prescaler divider
/16
/32
/64
/128
/256
482/709
2
C.

Figure 199. Independent watchdog block diagram

Prescaler register
Status register
IWDG_PR
IWDG_SR
8-bit
prescaler

Table 86. Min/max IWDG timeout period (in ms) at 40 kHz (LSI)

PR[2:0] bits
/4 0
/8 1
2
3
4
5
6 (or 7)
®
Section 25.15.2: Debug support for timers,
Reload register
IWDG_RLR
12-bit reload value
12-bit downcounter
voltage domain, still functional in Stop and
DD
Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF
0.1
0.2
0.4
0.8
1.6
3.2
6.4
RM0041 Rev 6
-M3 core halted), the IWDG counter
Key register
IWDG_KR
IWDG reset
409.6
819.2
1638.4
3276.8
6553.6
13107.2
26214.4
RM0041
MS19944V2
(1)