Enabling The Bus-Hold Protocol (8Xc196K X Only) - Intel 8XC196K Series User Manual

8XC196K x , J x , CA USER'S MANUAL
Symbol
T
HVCH
T
CLHAL
T
CLHAH
T
CLBRL
T
CLBRH
T
HALAZ
T
HAHAX
T
HALBZ
T
HAHBV
T
CLLH
When the external device is finished with the bus, it relinquishes control by driving HOLD# high.
In response, the 8XC196Kx drives HLDA# high and assumes control of the bus.
If the 8XC196Kx has a pending external bus cycle while it is in hold, it asserts BREQ# to request
control of the bus. After the external device responds by driving HOLD# high, the 8XC196Kx
exits hold and then deasserts BREQ# and HLDA#.
If the 8XC196Kx receives an interrupt request while it is in hold, the
8XC196Kx asserts INTOUT# only if it is executing from internal memory. If
the 8XC196Kx needs to access external memory, it asserts BREQ# and waits
until the external device deasserts HOLD# to assert INTOUT#. If the
8XC196Kx receives an interrupt request as it is going into hold (between the
time that an external device asserts HOLD# and the time that the 8XC196Kx
responds with HLDA#), the 8XC196Kx asserts INTOUT# and keeps it
asserted until the external device deasserts HOLD#.

15.5.1 Enabling the Bus-hold Protocol (8XC196K x Only)

To use the bus-hold protocol, you must configure P2.3/BREQ#, P2.5/HOLD#, and P2.6/HLDA#
to operate as special-function signals. BREQ# and HLDA# are active-low outputs; HOLD# is an
active-low input.
15-18
Table 15-3. HOLD#, HLDA# Timing Definitions
HOLD# Setup Time
CLKOUT Low to HLDA# Low
CLKOUT Low to HLDA# High
CLKOUT Low to BREQ# Low
CLKOUT Low to BREQ# High
HLDA# Low to Address Float
HLDA# High to Address No Longer Float
HLDA# Low to BHE#, INST, RD#, WR#, WRL#, WRH#
Weakly Driven
HLDA# High to BHE#, INST, RD#, WR#, WRL#, WRH# valid
Clock Falling to ALE Rising; Use to derive other timings.
NOTE
Parameter