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Table 4-5. CAN Peripheral SFRs — 8XC196CA Only (Continued)
Message 7
Addr
High (Odd) Byte
1E7EH
Reserved
1E7CH
CAN_MSG7DATA6
1E7AH
CAN_MSG7DATA4
1E78H
CAN_MSG7DATA2
1E76H
CAN_MSG7DATA0
1E74H
CAN_MSG7ID3
1E72H
CAN_MSG7ID1
1E70H
CAN_MSG7CON1
Message 6
Addr
High (Odd) Byte
1E6EH
Reserved
1E6CH
CAN_MSG6DATA6
1E6AH
CAN_MSG6DATA4
1E68H
CAN_MSG6DATA2
1E66H
CAN_MSG6DATA0
1E64H
CAN_MSG6ID3
1E62H
CAN_MSG6ID1
1E60H
CAN_MSG6CON1
Message 5 and Interrupts
Addr
High (Odd) Byte
1E5EH
CAN_INT
1E5CH
CAN_MSG5DATA6
1E5AH
CAN_MSG5DATA4
1E58H
CAN_MSG5DATA2
1E56H
CAN_MSG5DATA0
1E54H
CAN_MSG5ID3
1E52H
CAN_MSG5ID1
1E50H
CAN_MSG5CON1
Message 4 and Bit Timing 1
Addr
High (Odd) Byte
†
1E4EH
CAN_BTIME1
1E4CH
CAN_MSG4DATA6
1E4AH
CAN_MSG4DATA4
1E48H
CAN_MSG4DATA2
1E46H
CAN_MSG4DATA0
1E44H
CAN_MSG4ID3
1E42H
CAN_MSG4ID1
1E40H
CAN_MSG4CON1
†
The CCE bit in the control register (CAN_CON) must be set to enable write access to the bit timing registers
(CAN_BTIME0 and CAN_BTIME1).
Low (Even) Byte
CAN_MSG7DATA7
1E3EH
CAN_MSG7DATA5
1E3CH
CAN_MSG7DATA3
1E3AH
CAN_MSG7DATA1
1E38H
CAN_MSG7CFG
1E36H
CAN_MSG7ID2
1E34H
CAN_MSG7ID0
1E32H
CAN_MSG7CON0
1E30H
Low (Even) Byte
CAN_MSG6DATA7
1E2EH
CAN_MSG6DATA5
1E2CH
CAN_MSG6DATA3
1E2AH
CAN_MSG6DATA1
1E28H
CAN_MSG6CFG
1E26H
CAN_MSG6ID2
1E24H
CAN_MSG6ID0
1E22H
CAN_MSG6CON0
1E20H
Low (Even) Byte
CAN_MSG5DATA7
1E1EH
CAN_MSG5DATA5
1E1CH
CAN_MSG5DATA3
1E1AH
CAN_MSG5DATA1
1E18H
CAN_MSG5CFG
1E16H
CAN_MSG5ID2
1E14H
CAN_MSG5ID0
1E12H
CAN_MSG5CON0
1E10H
Low (Even) Byte
CAN_MSG4DATA7
1E0EH
CAN_MSG4DATA5
1E0CH
CAN_MSG4DATA3
1E0AH
CAN_MSG4DATA1
1E08H
CAN_MSG4CFG
1E06H
CAN_MSG4ID2
1E04H
CAN_MSG4ID0
1E02H
CAN_MSG4CON0
1E00H
MEMORY PARTITIONS
Message 3 and Bit Timing 0
Addr
High (Odd) Byte
†
CAN_BTIME0
CAN_MSG3DATA6
CAN_MSG3DATA4
CAN_MSG3DATA2
CAN_MSG3DATA0
CAN_MSG3ID3
CAN_MSG3ID1
CAN_MSG3CON1
Message 2
Addr
High (Odd) Byte
Reserved
CAN_MSG2DATA6
CAN_MSG2DATA4
CAN_MSG2DATA2
CAN_MSG2DATA0
CAN_MSG2ID3
CAN_MSG2ID1
CAN_MSG2CON1
Message 1
Addr
High (Odd) Byte
Reserved
CAN_MSG1DATA6
CAN_MSG1DATA4
CAN_MSG1DATA2
CAN_MSG1DATA0
CAN_MSG1ID3
CAN_MSG1ID1
CAN_MSG1CON1
Mask, Control, and Status
Addr
High (Odd) Byte
CAN_MSK15
CAN_MSK15
CAN_EGMSK
CAN_EGMSK
CAN_SGMSK
Reserved
Reserved
CAN_STAT
Low (Even) Byte
CAN_MSG3DATA7
CAN_MSG3DATA5
CAN_MSG3DATA3
CAN_MSG3DATA1
CAN_MSG3CFG
CAN_MSG3ID2
CAN_MSG3ID0
CAN_MSG3CON0
Low (Even) Byte
CAN_MSG2DATA7
CAN_MSG2DATA5
CAN_MSG2DATA3
CAN_MSG2DATA1
CAN_MSG2CFG
CAN_MSG2ID2
CAN_MSG2ID0
CAN_MSG2CON0
Low (Even) Byte
CAN_MSG1DATA7
CAN_MSG1DATA5
CAN_MSG1DATA3
CAN_MSG1DATA1
CAN_MSG1CFG
CAN_MSG1ID2
CAN_MSG1ID0
CAN_MSG1CON0
Low (Even) Byte
CAN_MSK15
CAN_MSK15
CAN_EGMSK
CAN_EGMSK
CAN_SGMSK
Reserved
Reserved
†
CAN_CON
4-9
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